[x64] Add disassembly tests for 256-bit instructions

A previous change (see ref) added a subset of 256-bit instructions to
the x64 assembler--this change adds a disassembly test for the added
instructions.

ref: https://chromium-review.googlesource.com/c/v8/v8/+/3123648
Change-Id: Ia56be7a7df636b8bf6c04f044912e914d949d19f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3133956
Auto-Submit: Andrew Brown <andrew.brown@intel.com>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/main@{#76711}

test/cctest/test-disasm-x64.cc

@@ -667,10 +667,15 @@ TEST(DisasmX64) {
 
       __ vmovdqa(xmm4, xmm5);
       __ vmovdqa(xmm4, Operand(rbx, rcx, times_4, 10000));
+      __ vmovdqa(ymm4, ymm5);
+      __ vmovdqa(xmm4, Operand(rbx, rcx, times_4, 10000));
 
       __ vmovdqu(xmm9, Operand(rbx, rcx, times_4, 10000));
       __ vmovdqu(Operand(rbx, rcx, times_4, 10000), xmm0);
       __ vmovdqu(xmm4, xmm5);
+      __ vmovdqu(ymm9, Operand(rbx, rcx, times_4, 10000));
+      __ vmovdqu(Operand(rbx, rcx, times_4, 10000), ymm0);
+      __ vmovdqu(ymm4, ymm5);
 
       __ vmovhlps(xmm1, xmm3, xmm5);
       __ vmovlps(xmm8, xmm9, Operand(rbx, rcx, times_4, 10000));
@@ -760,14 +765,18 @@ TEST(DisasmX64) {
 
 #define EMIT_SSE_UNOP_AVXINSTR(instruction, notUsed1, notUsed2) \
   __ v##instruction(xmm10, xmm1);                               \
-  __ v##instruction(xmm10, Operand(rbx, rcx, times_4, 10000));
+  __ v##instruction(xmm10, Operand(rbx, rcx, times_4, 10000));  \
+  __ v##instruction(ymm10, ymm1);                               \
+  __ v##instruction(ymm10, Operand(rbx, rcx, times_4, 10000));
 
       SSE_UNOP_INSTRUCTION_LIST(EMIT_SSE_UNOP_AVXINSTR)
 #undef EMIT_SSE_UNOP_AVXINSTR
 
-#define EMIT_SSE_BINOP_AVXINSTR(instruction, notUsed1, notUsed2) \
-  __ v##instruction(xmm10, xmm5, xmm1);                          \
-  __ v##instruction(xmm10, xmm5, Operand(rbx, rcx, times_4, 10000));
+#define EMIT_SSE_BINOP_AVXINSTR(instruction, notUsed1, notUsed2)     \
+  __ v##instruction(xmm10, xmm5, xmm1);                              \
+  __ v##instruction(xmm10, xmm5, Operand(rbx, rcx, times_4, 10000)); \
+  __ v##instruction(ymm10, ymm5, ymm1);                              \
+  __ v##instruction(ymm10, ymm5, Operand(rbx, rcx, times_4, 10000));
 
       SSE_BINOP_INSTRUCTION_LIST(EMIT_SSE_BINOP_AVXINSTR)
 #undef EMIT_SSE_BINOP_AVXINSTR
@@ -1048,6 +1057,33 @@ TEST(DisasmX64) {
 #endif
 }
 
+TEST(DisasmX64YMMRegister) {
+  if (!CpuFeatures::IsSupported(AVX)) return;
+  CcTest::InitializeVM();
+  Isolate* isolate = CcTest::i_isolate();
+  HandleScope scope(isolate);
+  v8::internal::byte buffer[8192];
+  Assembler assm(AssemblerOptions{},
+                 ExternalAssemblerBuffer(buffer, sizeof buffer));
+  CpuFeatureScope fscope(&assm, AVX);
+
+  __ vmovdqa(ymm0, ymm1);
+
+  base::Vector<char> actual = base::Vector<char>::New(37);
+  disasm::NameConverter converter;
+  disasm::Disassembler disassembler(converter);
+  disassembler.InstructionDecode(actual, buffer);
+#ifdef OBJECT_PRINT
+  fprintf(stdout, "Disassembled buffer: %s\n", actual.begin());
+#endif
+
+  base::Vector<const char> expected =
+      base::StaticCharVector("c5fd6fc1           vmovdqa ymm0,ymm1\0");
+  CHECK(expected == actual);
+
+  actual.Dispose();
+}
+
 #undef __
 
 }  // namespace internal