[arm][arm64] Remove dead code

Change-Id: I22a6d25fb1d7b8e0db13df4a0be46d2f4104d20c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2064394Reviewed-by: Georg Neis <neis@chromium.org>
Commit-Queue: Georgia Kouveli <georgia.kouveli@arm.com>
Cr-Commit-Position: refs/heads/master@{#66422}

src/codegen/arm/macro-assembler-arm.cc

@@ -852,13 +852,6 @@ void TurboAssembler::PushStandardFrame(Register function_reg) {
   add(fp, sp, Operand(offset));
 }
 
-int MacroAssembler::SafepointRegisterStackIndex(int reg_code) {
-  // The registers are pushed starting with the highest encoding,
-  // which means that lowest encodings are closest to the stack pointer.
-  DCHECK(reg_code >= 0 && reg_code < kNumSafepointRegisters);
-  return reg_code;
-}
-
 void TurboAssembler::VFPCanonicalizeNaN(const DwVfpRegister dst,
                                         const DwVfpRegister src,
                                         const Condition cond) {

src/codegen/arm/macro-assembler-arm.h

@@ -800,13 +800,6 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
                       Register actual_parameter_count, Label* done,
                       InvokeFlag flag);
 
-  // Compute memory operands for safepoint stack slots.
-  static int SafepointRegisterStackIndex(int reg_code);
-
-  // Needs access to SafepointRegisterStackIndex for compiled frame
-  // traversal.
-  friend class StandardFrame;
-
   DISALLOW_IMPLICIT_CONSTRUCTORS(MacroAssembler);
 };
 

src/codegen/arm/register-arm.h

@@ -63,7 +63,6 @@ const int kR9Available = 1;  // 1 if available to us, 0 if reserved
 
 // Register list in load/store instructions
 // Note that the bit values must match those used in actual instruction encoding
-const int kNumRegs = 16;
 
 // Caller-saved/arguments registers
 const RegList kJSCallerSaved = 1 << 0 |  // r0 a1
@@ -96,17 +95,6 @@ const int kNumCalleeSaved = 7 + kR9Available;
 // Double registers d8 to d15 are callee-saved.
 const int kNumDoubleCalleeSaved = 8;
 
-// Number of registers for which space is reserved in safepoints. Must be a
-// multiple of 8.
-// TODO(regis): Only 8 registers may actually be sufficient. Revisit.
-const int kNumSafepointRegisters = 16;
-
-// Define the list of registers actually saved at safepoints.
-// Note that the number of saved registers may be smaller than the reserved
-// space, i.e. kNumSafepointSavedRegisters <= kNumSafepointRegisters.
-const RegList kSafepointSavedRegisters = kJSCallerSaved | kCalleeSaved;
-const int kNumSafepointSavedRegisters = kNumJSCallerSaved + kNumCalleeSaved;
-
 enum RegisterCode {
 #define REGISTER_CODE(R) kRegCode_##R,
   GENERAL_REGISTERS(REGISTER_CODE)

src/codegen/arm64/assembler-arm64-inl.h

@@ -463,19 +463,6 @@ bool MemOperand::IsPreIndex() const { return addrmode_ == PreIndex; }
 
 bool MemOperand::IsPostIndex() const { return addrmode_ == PostIndex; }
 
-Operand MemOperand::OffsetAsOperand() const {
-  if (IsImmediateOffset()) {
-    return offset();
-  } else {
-    DCHECK(IsRegisterOffset());
-    if (extend() == NO_EXTEND) {
-      return Operand(regoffset(), shift(), shift_amount());
-    } else {
-      return Operand(regoffset(), extend(), shift_amount());
-    }
-  }
-}
-
 void Assembler::Unreachable() { debug("UNREACHABLE", __LINE__, BREAK); }
 
 Address Assembler::target_pointer_address_at(Address pc) {

src/codegen/arm64/assembler-arm64.cc

@@ -83,18 +83,6 @@ CPURegister CPURegList::PopHighestIndex() {
   return CPURegister::Create(index, size_, type_);
 }
 
-void CPURegList::RemoveCalleeSaved() {
-  if (type() == CPURegister::kRegister) {
-    Remove(GetCalleeSaved(RegisterSizeInBits()));
-  } else if (type() == CPURegister::kVRegister) {
-    Remove(GetCalleeSavedV(RegisterSizeInBits()));
-  } else {
-    DCHECK_EQ(type(), CPURegister::kNoRegister);
-    DCHECK(IsEmpty());
-    // The list must already be empty, so do nothing.
-  }
-}
-
 void CPURegList::Align() {
   // Use padreg, if necessary, to maintain stack alignment.
   if (Count() % 2 != 0) {
@@ -130,34 +118,6 @@ CPURegList CPURegList::GetCallerSavedV(int size) {
   return list;
 }
 
-// This function defines the list of registers which are associated with a
-// safepoint slot. Safepoint register slots are saved contiguously on the stack.
-// MacroAssembler::SafepointRegisterStackIndex handles mapping from register
-// code to index in the safepoint register slots. Any change here can affect
-// this mapping.
-CPURegList CPURegList::GetSafepointSavedRegisters() {
-  CPURegList list = CPURegList::GetCalleeSaved();
-  list.Combine(
-      CPURegList(CPURegister::kRegister, kXRegSizeInBits, kJSCallerSaved));
-
-  // Note that unfortunately we can't use symbolic names for registers and have
-  // to directly use register codes. This is because this function is used to
-  // initialize some static variables and we can't rely on register variables
-  // to be initialized due to static initialization order issues in C++.
-
-  // Drop ip0 and ip1 (i.e. x16 and x17), as they should not be expected to be
-  // preserved outside of the macro assembler.
-  list.Remove(16);
-  list.Remove(17);
-
-  // x18 is the platform register and is reserved for the use of platform ABIs.
-
-  // Add the link register (x30) to the safepoint list.
-  list.Combine(30);
-
-  return list;
-}
-
 // -----------------------------------------------------------------------------
 // Implementation of RelocInfo
 
@@ -291,31 +251,6 @@ bool Operand::NeedsRelocation(const Assembler* assembler) const {
   return !RelocInfo::IsNone(rmode);
 }
 
-MemOperand::PairResult MemOperand::AreConsistentForPair(
-    const MemOperand& operandA, const MemOperand& operandB,
-    int access_size_log2) {
-  DCHECK_GE(access_size_log2, 0);
-  DCHECK_LE(access_size_log2, 3);
-  // Step one: check that they share the same base, that the mode is Offset
-  // and that the offset is a multiple of access size.
-  if (operandA.base() != operandB.base() || (operandA.addrmode() != Offset) ||
-      (operandB.addrmode() != Offset) ||
-      ((operandA.offset() & ((1 << access_size_log2) - 1)) != 0)) {
-    return kNotPair;
-  }
-  // Step two: check that the offsets are contiguous and that the range
-  // is OK for ldp/stp.
-  if ((operandB.offset() == operandA.offset() + (1LL << access_size_log2)) &&
-      is_int7(operandA.offset() >> access_size_log2)) {
-    return kPairAB;
-  }
-  if ((operandA.offset() == operandB.offset() + (1LL << access_size_log2)) &&
-      is_int7(operandB.offset() >> access_size_log2)) {
-    return kPairBA;
-  }
-  return kNotPair;
-}
-
 // Assembler
 Assembler::Assembler(const AssemblerOptions& options,
                      std::unique_ptr<AssemblerBuffer> buffer)

src/codegen/arm64/assembler-arm64.h

@@ -154,20 +154,6 @@ class MemOperand {
   inline bool IsPreIndex() const;
   inline bool IsPostIndex() const;
 
-  // For offset modes, return the offset as an Operand. This helper cannot
-  // handle indexed modes.
-  inline Operand OffsetAsOperand() const;
-
-  enum PairResult {
-    kNotPair,  // Can't use a pair instruction.
-    kPairAB,   // Can use a pair instruction (operandA has lower address).
-    kPairBA    // Can use a pair instruction (operandB has lower address).
-  };
-  // Check if two MemOperand are consistent for stp/ldp use.
-  static PairResult AreConsistentForPair(const MemOperand& operandA,
-                                         const MemOperand& operandB,
-                                         int access_size_log2 = kXRegSizeLog2);
-
  private:
   Register base_;
   Register regoffset_;

src/codegen/arm64/constants-arm64.h

@@ -40,12 +40,8 @@ const int kNumberOfRegisters = 32;
 const int kNumberOfVRegisters = 32;
 // Callee saved registers are x19-x28.
 const int kNumberOfCalleeSavedRegisters = 10;
-const int kFirstCalleeSavedRegisterIndex = 19;
 // Callee saved FP registers are d8-d15.
 const int kNumberOfCalleeSavedVRegisters = 8;
-const int kFirstCalleeSavedVRegisterIndex = 8;
-// Callee saved registers with no specific purpose in JS are x19-x25.
-const size_t kJSCalleeSavedRegList = 0x03f80000;
 const int kWRegSizeInBits = 32;
 const int kWRegSizeInBitsLog2 = 5;
 const int kWRegSize = kWRegSizeInBits >> 3;

src/codegen/arm64/instructions-arm64.cc

@@ -310,28 +310,6 @@ void Instruction::SetImmLLiteral(Instruction* source) {
   SetInstructionBits(Mask(~mask) | imm);
 }
 
-// TODO(jbramley): We can't put this inline in the class because things like
-// xzr and Register are not defined in that header. Consider adding
-// instructions-arm64-inl.h to work around this.
-bool InstructionSequence::IsInlineData() const {
-  // Inline data is encoded as a single movz instruction which writes to xzr
-  // (x31).
-  return IsMovz() && SixtyFourBits() && (Rd() == kZeroRegCode);
-  // TODO(all): If we extend ::InlineData() to support bigger data, we need
-  // to update this method too.
-}
-
-// TODO(jbramley): We can't put this inline in the class because things like
-// xzr and Register are not defined in that header. Consider adding
-// instructions-arm64-inl.h to work around this.
-uint64_t InstructionSequence::InlineData() const {
-  DCHECK(IsInlineData());
-  uint64_t payload = ImmMoveWide();
-  // TODO(all): If we extend ::InlineData() to support bigger data, we need
-  // to update this method too.
-  return payload;
-}
-
 NEONFormatDecoder::NEONFormatDecoder(const Instruction* instr) {
   instrbits_ = instr->InstructionBits();
   SetFormatMaps(IntegerFormatMap());

src/codegen/arm64/instructions-arm64.h

@@ -463,20 +463,6 @@ class Instruction {
   void SetBranchImmTarget(Instruction* target);
 };
 
-// Where Instruction looks at instructions generated by the Assembler,
-// InstructionSequence looks at instructions sequences generated by the
-// MacroAssembler.
-class InstructionSequence : public Instruction {
- public:
-  static InstructionSequence* At(Address address) {
-    return reinterpret_cast<InstructionSequence*>(address);
-  }
-
-  // Sequences generated by MacroAssembler::InlineData().
-  bool IsInlineData() const;
-  uint64_t InlineData() const;
-};
-
 // Simulator/Debugger debug instructions ---------------------------------------
 // Each debug marker is represented by a HLT instruction. The immediate comment
 // field in the instruction is used to identify the type of debug marker. Each

src/codegen/arm64/macro-assembler-arm64-inl.h

@@ -1417,12 +1417,6 @@ void TurboAssembler::TestAndBranchIfAllClear(const Register& reg,
   }
 }
 
-void MacroAssembler::InlineData(uint64_t data) {
-  DCHECK(is_uint16(data));
-  InstructionAccurateScope scope(this, 1);
-  movz(xzr, data);
-}
-
 }  // namespace internal
 }  // namespace v8
 

src/codegen/arm64/macro-assembler-arm64.cc

@@ -2610,30 +2610,6 @@ void TurboAssembler::DecompressAnyTagged(const Register& destination,
   RecordComment("]");
 }
 
-int MacroAssembler::SafepointRegisterStackIndex(int reg_code) {
-  // Make sure the safepoint registers list is what we expect.
-  DCHECK_EQ(CPURegList::GetSafepointSavedRegisters().list(), 0x6FFCFFFF);
-
-  // Safepoint registers are stored contiguously on the stack, but not all the
-  // registers are saved. The following registers are excluded:
-  //  - x16 and x17 (ip0 and ip1) because they shouldn't be preserved outside of
-  //    the macro assembler.
-  //  - x31 (sp) because the system stack pointer doesn't need to be included
-  //    in safepoint registers.
-  //
-  // This function implements the mapping of register code to index into the
-  // safepoint register slots.
-  if ((reg_code >= 0) && (reg_code <= 15)) {
-    return reg_code;
-  } else if ((reg_code >= 18) && (reg_code <= 30)) {
-    // Skip ip0 and ip1.
-    return reg_code - 2;
-  } else {
-    // This register has no safepoint register slot.
-    UNREACHABLE();
-  }
-}
-
 void TurboAssembler::CheckPageFlag(const Register& object, int mask,
                                    Condition cc, Label* condition_met) {
   UseScratchRegisterScope temps(this);
@@ -2873,14 +2849,6 @@ void TurboAssembler::AssertUnreachable(AbortReason reason) {
   if (emit_debug_code()) Abort(reason);
 }
 
-void MacroAssembler::AssertRegisterIsRoot(Register reg, RootIndex index,
-                                          AbortReason reason) {
-  if (emit_debug_code()) {
-    CompareRoot(reg, index);
-    Check(eq, reason);
-  }
-}
-
 void TurboAssembler::Check(Condition cond, AbortReason reason) {
   Label ok;
   B(cond, &ok);

src/codegen/arm64/macro-assembler-arm64.h

@@ -18,12 +18,6 @@
 
 // Simulator specific helpers.
 #if USE_SIMULATOR
-// TODO(all): If possible automatically prepend an indicator like
-// UNIMPLEMENTED or LOCATION.
-#define ASM_UNIMPLEMENTED(message) __ Debug(message, __LINE__, NO_PARAM)
-#define ASM_UNIMPLEMENTED_BREAK(message) \
-  __ Debug(message, __LINE__,            \
-           FLAG_ignore_asm_unimplemented_break ? NO_PARAM : BREAK)
 #if DEBUG
 #define ASM_LOCATION(message) __ Debug("LOCATION: " message, __LINE__, NO_PARAM)
 #define ASM_LOCATION_IN_ASSEMBLER(message) \
@@ -33,8 +27,6 @@
 #define ASM_LOCATION_IN_ASSEMBLER(message)
 #endif
 #else
-#define ASM_UNIMPLEMENTED(message)
-#define ASM_UNIMPLEMENTED_BREAK(message)
 #define ASM_LOCATION(message)
 #define ASM_LOCATION_IN_ASSEMBLER(message)
 #endif
@@ -136,10 +128,6 @@ inline BranchType InvertBranchType(BranchType type) {
 enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET };
 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK };
 enum LinkRegisterStatus { kLRHasNotBeenSaved, kLRHasBeenSaved };
-enum TargetAddressStorageMode {
-  CAN_INLINE_TARGET_ADDRESS,
-  NEVER_INLINE_TARGET_ADDRESS
-};
 enum DiscardMoveMode { kDontDiscardForSameWReg, kDiscardForSameWReg };
 
 // The macro assembler supports moving automatically pre-shifted immediates for
@@ -1711,11 +1699,6 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // be aligned to 16 bytes.
   void PeekPair(const CPURegister& dst1, const CPURegister& dst2, int offset);
 
-  // Insert one or more instructions into the instruction stream that encode
-  // some caller-defined data. The instructions used will be executable with no
-  // side effects.
-  inline void InlineData(uint64_t data);
-
   // Preserve the callee-saved registers (as defined by AAPCS64).
   //
   // Higher-numbered registers are pushed before lower-numbered registers, and
@@ -1743,8 +1726,6 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
 
   // Helpers ------------------------------------------------------------------
 
-  static int SafepointRegisterStackIndex(int reg_code);
-
   template <typename Field>
   void DecodeField(Register dst, Register src) {
     static const int shift = Field::kShift;
@@ -1975,25 +1956,8 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // ---------------------------------------------------------------------------
   // Debugging.
 
-  void AssertRegisterIsRoot(
-      Register reg, RootIndex index,
-      AbortReason reason = AbortReason::kRegisterDidNotMatchExpectedRoot);
-
   void LoadNativeContextSlot(int index, Register dst);
 
-  // Far branches resolving.
-  //
-  // The various classes of branch instructions with immediate offsets have
-  // different ranges. While the Assembler will fail to assemble a branch
-  // exceeding its range, the MacroAssembler offers a mechanism to resolve
-  // branches to too distant targets, either by tweaking the generated code to
-  // use branch instructions with wider ranges or generating veneers.
-  //
-  // Currently branches to distant targets are resolved using unconditional
-  // branch isntructions with a range of +-128MB. If that becomes too little
-  // (!), the mechanism can be extended to generate special veneers for really
-  // far targets.
-
   DISALLOW_IMPLICIT_CONSTRUCTORS(MacroAssembler);
 };
 

src/codegen/arm64/register-arm64.h

@@ -71,23 +71,6 @@ namespace internal {
 
 constexpr int kRegListSizeInBits = sizeof(RegList) * kBitsPerByte;
 
-const int kNumRegs = kNumberOfRegisters;
-// Registers x0-x17 are caller-saved.
-const int kNumJSCallerSaved = 18;
-const RegList kJSCallerSaved = 0x3ffff;
-
-// Number of registers for which space is reserved in safepoints. Must be a
-// multiple of eight.
-// TODO(all): Refine this number.
-const int kNumSafepointRegisters = 32;
-
-// Define the list of registers actually saved at safepoints.
-// Note that the number of saved registers may be smaller than the reserved
-// space, i.e. kNumSafepointSavedRegisters <= kNumSafepointRegisters.
-#define kSafepointSavedRegisters CPURegList::GetSafepointSavedRegisters().list()
-#define kNumSafepointSavedRegisters \
-  CPURegList::GetSafepointSavedRegisters().Count()
-
 // Some CPURegister methods can return Register and VRegister types, so we
 // need to declare them in advance.
 class Register;
@@ -600,10 +583,6 @@ class V8_EXPORT_PRIVATE CPURegList {
   void Combine(int code);
   void Remove(int code);
 
-  // Remove all callee-saved registers from the list. This can be useful when
-  // preparing registers for an AAPCS64 function call, for example.
-  void RemoveCalleeSaved();
-
   // Align the list to 16 bytes.
   void Align();
 
@@ -620,9 +599,6 @@ class V8_EXPORT_PRIVATE CPURegList {
   static CPURegList GetCallerSaved(int size = kXRegSizeInBits);
   static CPURegList GetCallerSavedV(int size = kDRegSizeInBits);
 
-  // Registers saved as safepoints.
-  static CPURegList GetSafepointSavedRegisters();
-
   bool IsEmpty() const {
     return list_ == 0;
   }

src/flags/flag-definitions.h

@@ -1245,8 +1245,6 @@ DEFINE_INT(sim_stack_size, 2 * MB / KB,
            "in kBytes (default is 2 MB)")
 DEFINE_BOOL(log_colour, ENABLE_LOG_COLOUR,
             "When logging, try to use coloured output.")
-DEFINE_BOOL(ignore_asm_unimplemented_break, false,
-            "Don't break for ASM_UNIMPLEMENTED_BREAK macros.")
 DEFINE_BOOL(trace_sim_messages, false,
             "Trace simulator debug messages. Implied by --trace-sim.")