[riscv64] Add flag to control disassembling of C-ext

Also handling kArchStackPointerGreaterThan in AssembleArchBoolean

Change-Id: I253c1a6cb924364eead3b9fe58c7cf7d6f0696af
Bug: v8:11737
Bug: v8:11747
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2876854Reviewed-by: Jakob Gruber <jgruber@chromium.org>
Reviewed-by: Brice Dobry <brice.dobry@futurewei.com>
Commit-Queue: Brice Dobry <brice.dobry@futurewei.com>
Cr-Commit-Position: refs/heads/master@{#74543}

src/codegen/riscv64/assembler-riscv64.cc

@@ -747,7 +747,7 @@ bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
 }
 
 void Assembler::disassembleInstr(Instr instr) {
-  if (!FLAG_debug_riscv) return;
+  if (!FLAG_riscv_debug) return;
   disasm::NameConverter converter;
   disasm::Disassembler disasm(converter);
   EmbeddedVector<char, 128> disasm_buffer;

src/codegen/riscv64/constants-riscv64.cc

@@ -107,7 +107,7 @@ int FPURegisters::Number(const char* name) {
 
 InstructionBase::Type InstructionBase::InstructionType() const {
   // RV64C Instruction
-  if (IsShortInstruction()) {
+  if (FLAG_riscv_c_extension && IsShortInstruction()) {
     switch (InstructionBits() & kRvcOpcodeMask) {
       case RO_C_ADDI4SPN:
         return kCIWType;

src/codegen/riscv64/constants-riscv64.h

@@ -8,6 +8,7 @@
 #include "src/base/logging.h"
 #include "src/base/macros.h"
 #include "src/common/globals.h"
+#include "src/flags/flags.h"
 
 // UNIMPLEMENTED_ macro for RISCV.
 #ifdef DEBUG
@@ -732,12 +733,14 @@ class InstructionBase {
   }
 
   inline uint8_t InstructionSize() const {
-    return this->IsShortInstruction() ? kShortInstrSize : kInstrSize;
+    return (FLAG_riscv_c_extension && this->IsShortInstruction())
+               ? kShortInstrSize
+               : kInstrSize;
   }
 
   // Get the raw instruction bits.
   inline Instr InstructionBits() const {
-    if (this->IsShortInstruction()) {
+    if (FLAG_riscv_c_extension && this->IsShortInstruction()) {
       return 0x0000FFFF & (*reinterpret_cast<const ShortInstr*>(this));
     }
     return *reinterpret_cast<const Instr*>(this);

src/compiler/backend/riscv64/code-generator-riscv64.cc

@@ -2296,6 +2296,16 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
         UNREACHABLE();
     }
     return;
+  } else if (instr->arch_opcode() == kArchStackPointerGreaterThan) {
+    cc = FlagsConditionToConditionCmp(condition);
+    Register lhs_register = sp;
+    uint32_t offset;
+    if (ShouldApplyOffsetToStackCheck(instr, &offset)) {
+      lhs_register = i.TempRegister(0);
+      __ Sub64(lhs_register, sp, offset);
+    }
+    __ Sgtu(result, lhs_register, Operand(i.InputRegister(0)));
+    return;
   } else if (instr->arch_opcode() == kRiscvCmpD ||
              instr->arch_opcode() == kRiscvCmpS) {
     FPURegister left = i.InputOrZeroDoubleRegister(0);

src/flags/flag-definitions.h

@@ -1328,6 +1328,9 @@ DEFINE_BOOL(riscv_debug, false, "enable debug prints")
 
 DEFINE_BOOL(riscv_constant_pool, true,
             "enable constant pool (RISCV only)")
+
+DEFINE_BOOL(riscv_c_extension, false,
+            "enable compressed extension isa variant (RISCV only)")
 #endif
 
 // Controlling source positions for Torque/CSA code.

test/cctest/test-assembler-riscv64.cc

@@ -76,6 +76,16 @@ using F5 = void*(void* p0, void* p1, int p2, int p3, int p4);
     CHECK_EQ(expected_res, res);                                       \
   }
 
+#define UTEST_R1_FORM_WITH_RES_C(instr_name, in_type, out_type, rs1_val, \
+                                 expected_res)                           \
+  TEST(RISCV_UTEST_##instr_name) {                                       \
+    i::FLAG_riscv_c_extension = true;                                    \
+    CcTest::InitializeVM();                                              \
+    auto fn = [](MacroAssembler& assm) { __ instr_name(a0, a0); };       \
+    auto res = GenAndRunTest<out_type, in_type>(rs1_val, fn);            \
+    CHECK_EQ(expected_res, res);                                         \
+  }
+
 #define UTEST_I_FORM_WITH_RES(instr_name, type, rs1_val, imm12, expected_res) \
   TEST(RISCV_UTEST_##instr_name) {                                            \
     CcTest::InitializeVM();                                                   \
@@ -554,8 +564,8 @@ UTEST_CONV_F_FROM_I(fcvt_d_lu, uint64_t, double,
                     (double)(std::numeric_limits<uint64_t>::max()))
 
 // -- RV64C Standard Extension --
-UTEST_R1_FORM_WITH_RES(c_mv, int64_t, int64_t, 0x0f5600ab123400,
-                       0x0f5600ab123400)
+UTEST_R1_FORM_WITH_RES_C(c_mv, int64_t, int64_t, 0x0f5600ab123400,
+                         0x0f5600ab123400)
 
 // -- Assembler Pseudo Instructions --
 UTEST_R1_FORM_WITH_RES(mv, int64_t, int64_t, 0x0f5600ab123400, 0x0f5600ab123400)
@@ -1201,6 +1211,7 @@ TEST(NAN_BOX) {
 
 TEST(RVC_CI) {
   // Test RV64C extension CI type instructions.
+  i::FLAG_riscv_c_extension = true;
   CcTest::InitializeVM();
 
   // Test c.addi
@@ -1253,6 +1264,7 @@ TEST(RVC_CI) {
 }
 
 TEST(RVC_CIW) {
+  i::FLAG_riscv_c_extension = true;
   CcTest::InitializeVM();
 
   // Test c.addi4spn
@@ -1270,6 +1282,7 @@ TEST(RVC_CIW) {
 
 TEST(RVC_CR) {
   // Test RV64C extension CR type instructions.
+  i::FLAG_riscv_c_extension = true;
   CcTest::InitializeVM();
 
   // Test c.add
@@ -1285,6 +1298,7 @@ TEST(RVC_CR) {
 
 TEST(RVC_CA) {
   // Test RV64C extension CA type instructions.
+  i::FLAG_riscv_c_extension = true;
   CcTest::InitializeVM();
 
   // Test c.sub
@@ -1350,6 +1364,7 @@ TEST(RVC_CA) {
 
 TEST(RVC_LOAD_STORE_SP) {
   // Test RV64C extension fldsp/fsdsp, lwsp/swsp, ldsp/sdsp.
+  i::FLAG_riscv_c_extension = true;
   CcTest::InitializeVM();
 
   {
@@ -1382,6 +1397,8 @@ TEST(RVC_LOAD_STORE_SP) {
 
 TEST(RVC_LOAD_STORE_COMPRESSED) {
   // Test RV64C extension fld,  lw, ld.
+  i::FLAG_riscv_c_extension = true;
+
   CcTest::InitializeVM();
   Isolate* isolate = CcTest::i_isolate();
   HandleScope scope(isolate);
@@ -1462,6 +1479,7 @@ TEST(RVC_LOAD_STORE_COMPRESSED) {
 }
 
 TEST(RVC_JUMP) {
+  i::FLAG_riscv_c_extension = true;
   CcTest::InitializeVM();
 
   Label L, C;

test/cctest/test-disasm-riscv64.cc

@@ -465,6 +465,7 @@ TEST(PSEUDO) {
 }
 
 TEST(RV64C) {
+  i::FLAG_riscv_c_extension = true;
   SET_UP();
 
   COMPARE(c_nop(), "00000001       nop");