PPC [simd]: Add fp rounding and multiply-sum halfword to Sim

Change-Id: I9a1a236185614e41d6dba25331a0731666aed093
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2787187
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Reviewed-by: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73684}

src/codegen/ppc/constants-ppc.h

@@ -2912,7 +2912,11 @@ class Instruction {
       PPC_M_OPCODE_LIST(OPCODE_CASES)
       return static_cast<Opcode>(opcode);
     }
-
+    opcode = extcode | BitField(5, 0);
+    switch (opcode) {
+      PPC_VA_OPCODE_LIST(OPCODE_CASES)
+      return static_cast<Opcode>(opcode);
+    }
     opcode = extcode | BitField(10, 0);
     switch (opcode) {
       PPC_VX_OPCODE_LIST(OPCODE_CASES)
@@ -2965,11 +2969,6 @@ class Instruction {
       PPC_Z23_OPCODE_LIST(OPCODE_CASES)
       return static_cast<Opcode>(opcode);
     }
-    opcode = extcode | BitField(5, 0);
-    switch (opcode) {
-      PPC_VA_OPCODE_LIST(OPCODE_CASES)
-      return static_cast<Opcode>(opcode);
-    }
     opcode = extcode | BitField(5, 1);
     switch (opcode) {
       PPC_A_OPCODE_LIST(OPCODE_CASES)

src/execution/ppc/simulator-ppc.cc

@@ -4676,6 +4676,22 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
       VECTOR_FP_ROUNDING(double, nearbyint)
       break;
     }
+    case XVRSPIP: {
+      VECTOR_FP_ROUNDING(float, ceilf)
+      break;
+    }
+    case XVRSPIM: {
+      VECTOR_FP_ROUNDING(float, floorf)
+      break;
+    }
+    case XVRSPIZ: {
+      VECTOR_FP_ROUNDING(float, truncf)
+      break;
+    }
+    case XVRSPI: {
+      VECTOR_FP_ROUNDING(float, nearbyintf)
+      break;
+    }
 #undef VECTOR_FP_ROUNDING
     case VSEL: {
       int vrt = instr->RTValue();
@@ -4782,6 +4798,25 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
       }
       break;
     }
+    case VMSUMSHM: {
+      int vrt = instr->RTValue();
+      int vra = instr->RAValue();
+      int vrb = instr->RBValue();
+      int vrc = instr->RCValue();
+      FOR_EACH_LANE(i, int32_t) {
+        int16_t vra_1_val = get_simd_register_by_lane<int16_t>(vra, 2 * i);
+        int16_t vra_2_val =
+            get_simd_register_by_lane<int16_t>(vra, (2 * i) + 1);
+        int16_t vrb_1_val = get_simd_register_by_lane<int16_t>(vrb, 2 * i);
+        int16_t vrb_2_val =
+            get_simd_register_by_lane<int16_t>(vrb, (2 * i) + 1);
+        int32_t vrc_val = get_simd_register_by_lane<int32_t>(vrc, i);
+        int32_t temp1 = vra_1_val * vrb_1_val, temp2 = vra_2_val * vrb_2_val;
+        temp1 = temp1 + temp2 + vrc_val;
+        set_simd_register_by_lane<int32_t>(vrt, i, temp1);
+      }
+      break;
+    }
 #define VECTOR_UNARY_OP(type, op)                         \
   int t = instr->RTValue();                               \
   int b = instr->RBValue();                               \