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Commit c64c5542 authored by Vasili Skurydzin's avatar Vasili Skurydzin Committed by Commit Bot
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s390: Cleanup RSY formats in Assembler 

Change-Id: Ide53d314da54fa8b88d2b182627fa4c406250906
Reviewed-on: https://chromium-review.googlesource.com/1062410Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#53240}
parent 3637e15f
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Showing with 37 additions and 253 deletions
src/s390/assembler-s390.cc
View file @ c64c5542
...@@ -610,16 +610,6 @@ void Assembler::stm(Register r1, Register r2, const MemOperand& src) { ...@@ -610,16 +610,6 @@ void Assembler::stm(Register r1, Register r2, const MemOperand& src) {
rs_form(STM, r1, r2, src.rb(), src.offset()); rs_form(STM, r1, r2, src.rb(), src.offset());
} }
// 32-bit Store Multiple - long displacement (20-bits signed)
void Assembler::stmy(Register r1, Register r2, const MemOperand& src) {
rsy_form(STMY, r1, r2, src.rb(), src.offset());
}
// 64-bit Store Multiple - long displacement (20-bits signed)
void Assembler::stmg(Register r1, Register r2, const MemOperand& src) {
rsy_form(STMG, r1, r2, src.rb(), src.offset());
}
// Exception-generating instructions and debugging support. // Exception-generating instructions and debugging support.
// Stops with a non-negative code less than kNumOfWatchedStops support // Stops with a non-negative code less than kNumOfWatchedStops support
// enabling/disabling and a counter feature. See simulator-s390.h . // enabling/disabling and a counter feature. See simulator-s390.h .
...@@ -809,60 +799,6 @@ void Assembler::rsl_form(Opcode op, Length l1, Register b2, Disp d2) { ...@@ -809,60 +799,6 @@ void Assembler::rsl_form(Opcode op, Length l1, Register b2, Disp d2) {
emit6bytes(code); emit6bytes(code);
} }
// RSY1 format: <insn> R1,R3,D2(B2)
// +--------+----+----+----+-------------+--------+--------+
// | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
// +--------+----+----+----+-------------+--------+--------+
// 0 8 12 16 20 32 40 47
#define RSY1_FORM_EMIT(name, op) \
void Assembler::name(Register r1, Register r3, Register b2, Disp d2) { \
rsy_form(op, r1, r3, b2, d2); \
} \
void Assembler::name(Register r1, Register r3, const MemOperand& opnd) { \
name(r1, r3, opnd.getBaseRegister(), opnd.getDisplacement()); \
}
void Assembler::rsy_form(Opcode op, Register r1, Register r3, Register b2,
const Disp d2) {
DCHECK(is_int20(d2));
DCHECK(is_uint16(op));
uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
(static_cast<uint64_t>(r1.code())) * B36 |
(static_cast<uint64_t>(r3.code())) * B32 |
(static_cast<uint64_t>(b2.code())) * B28 |
(static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
(static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
(static_cast<uint64_t>(op & 0x00FF));
emit6bytes(code);
}
// RSY2 format: <insn> R1,M3,D2(B2)
// +--------+----+----+----+-------------+--------+--------+
// | OpCode | R1 | M3 | B2 | DL2 | DH2 | OpCode |
// +--------+----+----+----+-------------+--------+--------+
// 0 8 12 16 20 32 40 47
#define RSY2_FORM_EMIT(name, op) \
void Assembler::name(Register r1, Condition m3, Register b2, Disp d2) { \
rsy_form(op, r1, m3, b2, d2); \
} \
void Assembler::name(Register r1, Condition m3, const MemOperand& opnd) { \
name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement()); \
}
void Assembler::rsy_form(Opcode op, Register r1, Condition m3, Register b2,
const Disp d2) {
DCHECK(is_int20(d2));
DCHECK(is_uint16(op));
uint64_t code = (static_cast<uint64_t>(op & 0xFF00)) * B32 |
(static_cast<uint64_t>(r1.code())) * B36 |
(static_cast<uint64_t>(m3)) * B32 |
(static_cast<uint64_t>(b2.code())) * B28 |
(static_cast<uint64_t>(d2 & 0x0FFF)) * B16 |
(static_cast<uint64_t>(d2 & 0x0FF000)) >> 4 |
(static_cast<uint64_t>(op & 0x00FF));
emit6bytes(code);
}
// RXE format: <insn> R1,D2(X2,B2) // RXE format: <insn> R1,D2(X2,B2)
// +--------+----+----+----+-------------+--------+--------+ // +--------+----+----+----+-------------+--------+--------+
// | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | // | OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
...@@ -1350,16 +1286,6 @@ void Assembler::locgr(Condition m3, Register r1, Register r2) { ...@@ -1350,16 +1286,6 @@ void Assembler::locgr(Condition m3, Register r1, Register r2) {
rrf2_form(LOCGR << 16 | m3 * B12 | r1.code() * B4 | r2.code()); rrf2_form(LOCGR << 16 | m3 * B12 | r1.code() * B4 | r2.code());
} }
// Load On Condition R-M (32)
void Assembler::loc(Condition m3, Register r1, const MemOperand& src) {
rsy_form(LOC, r1, m3, src.rb(), src.offset());
}
// Load On Condition R-M (64)
void Assembler::locg(Condition m3, Register r1, const MemOperand& src) {
rsy_form(LOCG, r1, m3, src.rb(), src.offset());
}
// ------------------- // -------------------
// Branch Instructions // Branch Instructions
// ------------------- // -------------------
...@@ -1639,40 +1565,6 @@ void Assembler::EnsureSpaceFor(int space_needed) { ...@@ -1639,40 +1565,6 @@ void Assembler::EnsureSpaceFor(int space_needed) {
} }
} }
// Rotate Left Single Logical (32)
void Assembler::rll(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(RLL, r1, r3, opnd, 0);
}
// Rotate Left Single Logical (32)
void Assembler::rll(Register r1, Register r3, const Operand& opnd) {
rsy_form(RLL, r1, r3, r0, opnd.immediate());
}
// Rotate Left Single Logical (32)
void Assembler::rll(Register r1, Register r3, Register r2,
const Operand& opnd) {
rsy_form(RLL, r1, r3, r2, opnd.immediate());
}
// Rotate Left Single Logical (64)
void Assembler::rllg(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(RLLG, r1, r3, opnd, 0);
}
// Rotate Left Single Logical (64)
void Assembler::rllg(Register r1, Register r3, const Operand& opnd) {
rsy_form(RLLG, r1, r3, r0, opnd.immediate());
}
// Rotate Left Single Logical (64)
void Assembler::rllg(Register r1, Register r3, Register r2,
const Operand& opnd) {
rsy_form(RLLG, r1, r3, r2, opnd.immediate());
}
// Shift Left Single Logical (32) // Shift Left Single Logical (32)
void Assembler::sll(Register r1, Register opnd) { void Assembler::sll(Register r1, Register opnd) {
DCHECK(opnd != r0); DCHECK(opnd != r0);
...@@ -1684,28 +1576,6 @@ void Assembler::sll(Register r1, const Operand& opnd) { ...@@ -1684,28 +1576,6 @@ void Assembler::sll(Register r1, const Operand& opnd) {
rs_form(SLL, r1, r0, r0, opnd.immediate()); rs_form(SLL, r1, r0, r0, opnd.immediate());
} }
// Shift Left Single Logical (32)
void Assembler::sllk(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SLLK, r1, r3, opnd, 0);
}
// Shift Left Single Logical (32)
void Assembler::sllk(Register r1, Register r3, const Operand& opnd) {
rsy_form(SLLK, r1, r3, r0, opnd.immediate());
}
// Shift Left Single Logical (64)
void Assembler::sllg(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SLLG, r1, r3, opnd, 0);
}
// Shift Left Single Logical (64)
void Assembler::sllg(Register r1, Register r3, const Operand& opnd) {
rsy_form(SLLG, r1, r3, r0, opnd.immediate());
}
// Shift Left Double Logical (64) // Shift Left Double Logical (64)
void Assembler::sldl(Register r1, Register b2, const Operand& opnd) { void Assembler::sldl(Register r1, Register b2, const Operand& opnd) {
DCHECK_EQ(r1.code() % 2, 0); DCHECK_EQ(r1.code() % 2, 0);
...@@ -1735,28 +1605,6 @@ void Assembler::srl(Register r1, const Operand& opnd) { ...@@ -1735,28 +1605,6 @@ void Assembler::srl(Register r1, const Operand& opnd) {
rs_form(SRL, r1, r0, r0, opnd.immediate()); rs_form(SRL, r1, r0, r0, opnd.immediate());
} }
// Shift Right Single Logical (32)
void Assembler::srlk(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SRLK, r1, r3, opnd, 0);
}
// Shift Right Single Logical (32)
void Assembler::srlk(Register r1, Register r3, const Operand& opnd) {
rsy_form(SRLK, r1, r3, r0, opnd.immediate());
}
// Shift Right Single Logical (64)
void Assembler::srlg(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SRLG, r1, r3, opnd, 0);
}
// Shift Right Single Logical (64)
void Assembler::srlg(Register r1, Register r3, const Operand& opnd) {
rsy_form(SRLG, r1, r3, r0, opnd.immediate());
}
// Shift Left Single (32) // Shift Left Single (32)
void Assembler::sla(Register r1, Register opnd) { void Assembler::sla(Register r1, Register opnd) {
DCHECK(opnd != r0); DCHECK(opnd != r0);
...@@ -1768,28 +1616,6 @@ void Assembler::sla(Register r1, const Operand& opnd) { ...@@ -1768,28 +1616,6 @@ void Assembler::sla(Register r1, const Operand& opnd) {
rs_form(SLA, r1, r0, r0, opnd.immediate()); rs_form(SLA, r1, r0, r0, opnd.immediate());
} }
// Shift Left Single (32)
void Assembler::slak(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SLAK, r1, r3, opnd, 0);
}
// Shift Left Single (32)
void Assembler::slak(Register r1, Register r3, const Operand& opnd) {
rsy_form(SLAK, r1, r3, r0, opnd.immediate());
}
// Shift Left Single (64)
void Assembler::slag(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SLAG, r1, r3, opnd, 0);
}
// Shift Left Single (64)
void Assembler::slag(Register r1, Register r3, const Operand& opnd) {
rsy_form(SLAG, r1, r3, r0, opnd.immediate());
}
// Shift Right Single (32) // Shift Right Single (32)
void Assembler::sra(Register r1, Register opnd) { void Assembler::sra(Register r1, Register opnd) {
DCHECK(opnd != r0); DCHECK(opnd != r0);
...@@ -1801,27 +1627,6 @@ void Assembler::sra(Register r1, const Operand& opnd) { ...@@ -1801,27 +1627,6 @@ void Assembler::sra(Register r1, const Operand& opnd) {
rs_form(SRA, r1, r0, r0, opnd.immediate()); rs_form(SRA, r1, r0, r0, opnd.immediate());
} }
// Shift Right Single (32)
void Assembler::srak(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SRAK, r1, r3, opnd, 0);
}
// Shift Right Single (32)
void Assembler::srak(Register r1, Register r3, const Operand& opnd) {
rsy_form(SRAK, r1, r3, r0, opnd.immediate());
}
// Shift Right Single (64)
void Assembler::srag(Register r1, Register r3, Register opnd) {
DCHECK(opnd != r0);
rsy_form(SRAG, r1, r3, opnd, 0);
}
void Assembler::srag(Register r1, Register r3, const Operand& opnd) {
rsy_form(SRAG, r1, r3, r0, opnd.immediate());
}
// Shift Right Double // Shift Right Double
void Assembler::srda(Register r1, const Operand& opnd) { void Assembler::srda(Register r1, const Operand& opnd) {
DCHECK_EQ(r1.code() % 2, 0); DCHECK_EQ(r1.code() % 2, 0);
...@@ -1862,31 +1667,11 @@ void Assembler::lm(Register r1, Register r2, const MemOperand& src) { ...@@ -1862,31 +1667,11 @@ void Assembler::lm(Register r1, Register r2, const MemOperand& src) {
rs_form(LM, r1, r2, src.rb(), src.offset()); rs_form(LM, r1, r2, src.rb(), src.offset());
} }
// 32-bit Load Multiple - long displacement (20-bits signed)
void Assembler::lmy(Register r1, Register r2, const MemOperand& src) {
rsy_form(LMY, r1, r2, src.rb(), src.offset());
}
// 64-bit Load Multiple - long displacement (20-bits signed)
void Assembler::lmg(Register r1, Register r2, const MemOperand& src) {
rsy_form(LMG, r1, r2, src.rb(), src.offset());
}
// 32-bit Compare and Swap // 32-bit Compare and Swap
void Assembler::cs(Register r1, Register r2, const MemOperand& src) { void Assembler::cs(Register r1, Register r2, const MemOperand& src) {
rs_form(CS, r1, r2, src.rb(), src.offset()); rs_form(CS, r1, r2, src.rb(), src.offset());
} }
// 32-bit Compare and Swap
void Assembler::csy(Register r1, Register r2, const MemOperand& src) {
rsy_form(CSY, r1, r2, src.rb(), src.offset());
}
// 64-bit Compare and Swap
void Assembler::csg(Register r1, Register r2, const MemOperand& src) {
rsy_form(CSG, r1, r2, src.rb(), src.offset());
}
// Move integer (32) // Move integer (32)
void Assembler::mvhi(const MemOperand& opnd1, const Operand& i2) { void Assembler::mvhi(const MemOperand& opnd1, const Operand& i2) {
sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2);
......
src/s390/assembler-s390.h
View file @ c64c5542
...@@ -840,6 +840,43 @@ class Assembler : public AssemblerBase { ...@@ -840,6 +840,43 @@ class Assembler : public AssemblerBase {
} }
#undef DECLARE_S390_RXY_INSTRUCTIONS #undef DECLARE_S390_RXY_INSTRUCTIONS
inline void rsy_form(Opcode op, int f1, int f2, int f3, const int f4) {
DCHECK(is_int20(f4));
DCHECK(is_uint16(op));
uint64_t code = (getfield<uint64_t, 6, 0, 8>(op >> 8) |
getfield<uint64_t, 6, 8, 12>(f1) |
getfield<uint64_t, 6, 12, 16>(f2) |
getfield<uint64_t, 6, 16, 20>(f3) |
getfield<uint64_t, 6, 20, 32>(f4 & 0x0fff) |
getfield<uint64_t, 6, 32, 40>(f4 >> 12) |
getfield<uint64_t, 6, 40, 48>(op & 0xff));
emit6bytes(code);
}
#define DECLARE_S390_RSY_A_INSTRUCTIONS(name, op_name, op_value) \
void name(Register r1, Register r3, Register b2, Disp d2 = 0) { \
rsy_form(op_name, r1.code(), r3.code(), b2.code(), d2); \
} \
void name(Register r1, Register r3, Operand d2) { \
DCHECK_NE(d2.immediate(), 0); \
name(r1, r3, r0, d2.immediate()); \
} \
void name(Register r1, Register r3, const MemOperand& opnd) { \
name(r1, r3, opnd.getBaseRegister(), opnd.getDisplacement()); \
}
S390_RSY_A_OPCODE_LIST(DECLARE_S390_RSY_A_INSTRUCTIONS);
#undef DECLARE_S390_RSY_A_INSTRUCTIONS
#define DECLARE_S390_RSY_B_INSTRUCTIONS(name, op_name, op_value) \
void name(Register r1, Condition m3, Register b2, Disp d2) { \
rsy_form(op_name, r1.code(), m3, b2.code(), d2); \
} \
void name(Register r1, Condition m3, const MemOperand& opnd) { \
name(r1, m3, opnd.getBaseRegister(), opnd.getDisplacement()); \
}
S390_RSY_B_OPCODE_LIST(DECLARE_S390_RSY_B_INSTRUCTIONS);
#undef DECLARE_S390_RSY_B_INSTRUCTIONS
// Helper for unconditional branch to Label with update to save register // Helper for unconditional branch to Label with update to save register
void b(Register r, Label* l) { void b(Register r, Label* l) {
int32_t halfwords = branch_offset(l) / 2; int32_t halfwords = branch_offset(l) / 2;
...@@ -1120,21 +1157,15 @@ class Assembler : public AssemblerBase { ...@@ -1120,21 +1157,15 @@ class Assembler : public AssemblerBase {
// Load Multiple Instructions // Load Multiple Instructions
void lm(Register r1, Register r2, const MemOperand& src); void lm(Register r1, Register r2, const MemOperand& src);
void lmy(Register r1, Register r2, const MemOperand& src);
void lmg(Register r1, Register r2, const MemOperand& src);
// Load On Condition Instructions // Load On Condition Instructions
void locr(Condition m3, Register r1, Register r2); void locr(Condition m3, Register r1, Register r2);
void locgr(Condition m3, Register r1, Register r2); void locgr(Condition m3, Register r1, Register r2);
void loc(Condition m3, Register r1, const MemOperand& src);
void locg(Condition m3, Register r1, const MemOperand& src);
// Store Instructions // Store Instructions
// Store Multiple Instructions // Store Multiple Instructions
void stm(Register r1, Register r2, const MemOperand& src); void stm(Register r1, Register r2, const MemOperand& src);
void stmy(Register r1, Register r2, const MemOperand& src);
void stmg(Register r1, Register r2, const MemOperand& src);
// Compare Instructions // Compare Instructions
void chi(Register r, const Operand& opnd); void chi(Register r, const Operand& opnd);
...@@ -1147,50 +1178,24 @@ class Assembler : public AssemblerBase { ...@@ -1147,50 +1178,24 @@ class Assembler : public AssemblerBase {
// Compare and Swap Instructions // Compare and Swap Instructions
void cs(Register r1, Register r2, const MemOperand& src); void cs(Register r1, Register r2, const MemOperand& src);
void csy(Register r1, Register r2, const MemOperand& src);
void csg(Register r1, Register r2, const MemOperand& src);
// Test Under Mask Instructions // Test Under Mask Instructions
void tm(const MemOperand& mem, const Operand& imm); void tm(const MemOperand& mem, const Operand& imm);
void tmy(const MemOperand& mem, const Operand& imm); void tmy(const MemOperand& mem, const Operand& imm);
// Rotate Instructions
void rll(Register r1, Register r3, Register opnd);
void rll(Register r1, Register r3, const Operand& opnd);
void rll(Register r1, Register r3, Register r2, const Operand& opnd);
void rllg(Register r1, Register r3, const Operand& opnd);
void rllg(Register r1, Register r3, const Register opnd);
void rllg(Register r1, Register r3, Register r2, const Operand& opnd);
// Shift Instructions (32) // Shift Instructions (32)
void sll(Register r1, Register opnd); void sll(Register r1, Register opnd);
void sll(Register r1, const Operand& opnd); void sll(Register r1, const Operand& opnd);
void sllk(Register r1, Register r3, Register opnd);
void sllk(Register r1, Register r3, const Operand& opnd);
void srl(Register r1, Register opnd); void srl(Register r1, Register opnd);
void srl(Register r1, const Operand& opnd); void srl(Register r1, const Operand& opnd);
void srlk(Register r1, Register r3, Register opnd);
void srlk(Register r1, Register r3, const Operand& opnd);
void sra(Register r1, Register opnd); void sra(Register r1, Register opnd);
void sra(Register r1, const Operand& opnd); void sra(Register r1, const Operand& opnd);
void srak(Register r1, Register r3, Register opnd);
void srak(Register r1, Register r3, const Operand& opnd);
void sla(Register r1, Register opnd); void sla(Register r1, Register opnd);
void sla(Register r1, const Operand& opnd); void sla(Register r1, const Operand& opnd);
void slak(Register r1, Register r3, Register opnd);
void slak(Register r1, Register r3, const Operand& opnd);
// Shift Instructions (64) // Shift Instructions (64)
void sllg(Register r1, Register r3, const Operand& opnd);
void sllg(Register r1, Register r3, const Register opnd);
void srlg(Register r1, Register r3, const Operand& opnd);
void srlg(Register r1, Register r3, const Register opnd);
void srag(Register r1, Register r3, const Operand& opnd);
void srag(Register r1, Register r3, const Register opnd);
void srda(Register r1, const Operand& opnd); void srda(Register r1, const Operand& opnd);
void srdl(Register r1, const Operand& opnd); void srdl(Register r1, const Operand& opnd);
void slag(Register r1, Register r3, const Operand& opnd);
void slag(Register r1, Register r3, const Register opnd);
void sldl(Register r1, Register b2, const Operand& opnd); void sldl(Register r1, Register b2, const Operand& opnd);
void srdl(Register r1, Register b2, const Operand& opnd); void srdl(Register r1, Register b2, const Operand& opnd);
void srda(Register r1, Register b2, const Operand& opnd); void srda(Register r1, Register b2, const Operand& opnd);
...@@ -1541,12 +1546,6 @@ class Assembler : public AssemblerBase { ...@@ -1541,12 +1546,6 @@ class Assembler : public AssemblerBase {
inline void rsi_form(Opcode op, Register r1, Register r3, const Operand& i2); inline void rsi_form(Opcode op, Register r1, Register r3, const Operand& i2);
inline void rsl_form(Opcode op, Length l1, Register b2, Disp d2); inline void rsl_form(Opcode op, Length l1, Register b2, Disp d2);
inline void rsy_form(Opcode op, Register r1, Register r3, Register b2,
const Disp d2);
inline void rsy_form(Opcode op, Register r1, Condition m3, Register b2,
const Disp d2);
inline void rxe_form(Opcode op, Register r1, Register x2, Register b2, inline void rxe_form(Opcode op, Register r1, Register x2, Register b2,
Disp d2); Disp d2);
......
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