Commit c6446b23 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

S390 [liftoff]: Implement simd replace lane ops

Change-Id: I00da20528553e4135681790998c03126931bca9a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3042719
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Reviewed-by: 's avatarMichael Achenbach <machenbach@chromium.org>
Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75883}
parent 74e984a7
......@@ -5158,6 +5158,58 @@ void TurboAssembler::I8x16ExtractLaneS(Register dst, Simd128Register src,
lgbr(dst, r0);
}
void TurboAssembler::F64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2,
uint8_t imm_lane_idx) {
vlgv(r0, src2, MemOperand(r0, 0), Condition(3));
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, r0, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
}
void TurboAssembler::F32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2,
uint8_t imm_lane_idx) {
vlgv(r0, src2, MemOperand(r0, 0), Condition(2));
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, r0, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
}
void TurboAssembler::I64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, src2, MemOperand(r0, 1 - imm_lane_idx), Condition(3));
}
void TurboAssembler::I32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, src2, MemOperand(r0, 3 - imm_lane_idx), Condition(2));
}
void TurboAssembler::I16x8ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, src2, MemOperand(r0, 7 - imm_lane_idx), Condition(1));
}
void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx) {
if (src1 != dst) {
vlr(dst, src1, Condition(0), Condition(0), Condition(0));
}
vlvg(dst, src2, MemOperand(r0, 15 - imm_lane_idx), Condition(0));
}
} // namespace internal
} // namespace v8
......
......@@ -1054,6 +1054,18 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
uint8_t imm_lane_idx);
void I8x16ExtractLaneS(Register dst, Simd128Register src,
uint8_t imm_lane_idx);
void F64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2, uint8_t imm_lane_idx);
void F32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
DoubleRegister src2, uint8_t imm_lane_idx);
void I64x2ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
void I32x4ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
void I16x8ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
void I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
// ---------------------------------------------------------------------------
// Pointer compression Support
......
......@@ -2517,72 +2517,25 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
SIMD_EXTRACT_LANE_LIST(EMIT_SIMD_EXTRACT_LANE)
#undef EMIT_SIMD_EXTRACT_LANE
#undef SIMD_EXTRACT_LANE_LIST
// vector replace element
case kS390_F64x2ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
__ vlgv(kScratchReg, i.InputDoubleRegister(2), MemOperand(r0, 0),
Condition(3));
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(dst, kScratchReg, MemOperand(r0, 1 - i.InputInt8(1)),
Condition(3));
break;
}
case kS390_F32x4ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
__ vlgv(kScratchReg, i.InputDoubleRegister(2), MemOperand(r0, 0),
Condition(2));
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(dst, kScratchReg, MemOperand(r0, 3 - i.InputInt8(1)),
Condition(2));
break;
}
case kS390_I64x2ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(dst, i.InputRegister(2), MemOperand(r0, 1 - i.InputInt8(1)),
Condition(3));
break;
}
case kS390_I32x4ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(dst, i.InputRegister(2), MemOperand(r0, 3 - i.InputInt8(1)),
Condition(2));
break;
}
case kS390_I16x8ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(dst, i.InputRegister(2), MemOperand(r0, 7 - i.InputInt8(1)),
Condition(1));
break;
}
case kS390_I8x16ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(dst, i.InputRegister(2), MemOperand(r0, 15 - i.InputInt8(1)),
Condition(0));
break;
}
// vector binops
#define SIMD_REPLACE_LANE_LIST(V) \
V(F64x2ReplaceLane, DoubleRegister) \
V(F32x4ReplaceLane, DoubleRegister) \
V(I64x2ReplaceLane, Register) \
V(I32x4ReplaceLane, Register) \
V(I16x8ReplaceLane, Register) \
V(I8x16ReplaceLane, Register)
#define EMIT_SIMD_REPLACE_LANE(name, stype) \
case kS390_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.Input##stype(2), i.InputInt8(1)); \
break; \
}
SIMD_REPLACE_LANE_LIST(EMIT_SIMD_REPLACE_LANE)
#undef EMIT_SIMD_REPLACE_LANE
#undef SIMD_REPLACE_LANE_LIST
// vector binops
case kS390_F64x2Add: {
__ vfa(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
......
......@@ -2178,6 +2178,24 @@ SIMD_EXTRACT_LANE_LIST(EMIT_SIMD_EXTRACT_LANE)
#undef EMIT_SIMD_EXTRACT_LANE
#undef SIMD_EXTRACT_LANE_LIST
#define SIMD_REPLACE_LANE_LIST(V) \
V(f64x2_replace_lane, F64x2ReplaceLane, fp) \
V(f32x4_replace_lane, F32x4ReplaceLane, fp) \
V(i64x2_replace_lane, I64x2ReplaceLane, gp) \
V(i32x4_replace_lane, I32x4ReplaceLane, gp) \
V(i16x8_replace_lane, I16x8ReplaceLane, gp) \
V(i8x16_replace_lane, I8x16ReplaceLane, gp)
#define EMIT_SIMD_REPLACE_LANE(name, op, stype) \
void LiftoffAssembler::emit_##name( \
LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, \
uint8_t imm_lane_idx) { \
op(dst.fp(), src1.fp(), src2.stype(), imm_lane_idx); \
}
SIMD_REPLACE_LANE_LIST(EMIT_SIMD_REPLACE_LANE)
#undef EMIT_SIMD_REPLACE_LANE
#undef SIMD_REPLACE_LANE_LIST
void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
Register offset_reg, uintptr_t offset_imm,
LoadType type,
......@@ -2206,13 +2224,6 @@ void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i8x16_swizzle");
}
void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
uint8_t imm_lane_idx) {
bailout(kUnsupportedArchitecture, "emit_f64x2replacelane");
}
void LiftoffAssembler::emit_f64x2_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f64x2_abs");
......@@ -2307,13 +2318,6 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
bailout(kSimd, "f64x2.promote_low_f32x4");
}
void LiftoffAssembler::emit_f32x4_replace_lane(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
uint8_t imm_lane_idx) {
bailout(kUnsupportedArchitecture, "emit_f32x4replacelane");
}
void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_f32x4_abs");
......@@ -2393,13 +2397,6 @@ void LiftoffAssembler::emit_f32x4_pmax(LiftoffRegister dst, LiftoffRegister lhs,
bailout(kSimd, "pmax unimplemented");
}
void LiftoffAssembler::emit_i64x2_replace_lane(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
uint8_t imm_lane_idx) {
bailout(kUnsupportedArchitecture, "emit_i64x2replacelane");
}
void LiftoffAssembler::emit_i64x2_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i64x2neg");
......@@ -2506,13 +2503,6 @@ void LiftoffAssembler::emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst,
bailout(kSimd, "i64x2_extmul_high_i32x4_u unsupported");
}
void LiftoffAssembler::emit_i32x4_replace_lane(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
uint8_t imm_lane_idx) {
bailout(kUnsupportedArchitecture, "emit_i32x4replacelane");
}
void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i32x4neg");
......@@ -2749,13 +2739,6 @@ void LiftoffAssembler::emit_i16x8_max_u(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i16x8_max_u");
}
void LiftoffAssembler::emit_i16x8_replace_lane(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
uint8_t imm_lane_idx) {
bailout(kUnsupportedArchitecture, "emit_i16x8replacelane");
}
void LiftoffAssembler::emit_i16x8_extadd_pairwise_i8x16_s(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i16x8.extadd_pairwise_i8x16_s");
......@@ -2809,13 +2792,6 @@ void LiftoffAssembler::emit_i8x16_popcnt(LiftoffRegister dst,
bailout(kSimd, "i8x16.popcnt");
}
void LiftoffAssembler::emit_i8x16_replace_lane(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2,
uint8_t imm_lane_idx) {
bailout(kUnsupportedArchitecture, "emit_i8x16replacelane");
}
void LiftoffAssembler::emit_i8x16_neg(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kUnsupportedArchitecture, "emit_i8x16neg");
......
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