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Commit c605ea03 authored by sampsong's avatar sampsong Committed by Commit bot
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PPC: Add OPCODE_LIST macro 

BUG=

R=bjaideep@ca.ibm.com, jyan@ca.ibm.com, joransiu@ca.ibm.com

Review-Url: https://codereview.chromium.org/2710153002
Cr-Commit-Position: refs/heads/master@{#43421}
parent 18f423a9
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Showing with 2536 additions and 300 deletions
src/ppc/assembler-ppc-inl.h
View file @ c605ea03
......@@ -477,9 +477,9 @@ Address Assembler::target_address_at(Address pc, Address constant_pool) {
#if V8_TARGET_ARCH_PPC64
const int kLoadIntptrOpcode = LD;
const uint32_t kLoadIntptrOpcode = LD;
#else
const int kLoadIntptrOpcode = LWZ;
const uint32_t kLoadIntptrOpcode = LWZ;
#endif
// Constant pool load sequence detection:
......@@ -492,7 +492,7 @@ const int kLoadIntptrOpcode = LWZ;
bool Assembler::IsConstantPoolLoadStart(Address pc,
ConstantPoolEntry::Access* access) {
Instr instr = instr_at(pc);
int opcode = instr & kOpcodeMask;
uint32_t opcode = instr & kOpcodeMask;
if (!GetRA(instr).is(kConstantPoolRegister)) return false;
bool overflowed = (opcode == ADDIS);
#ifdef DEBUG
......@@ -512,7 +512,7 @@ bool Assembler::IsConstantPoolLoadStart(Address pc,
bool Assembler::IsConstantPoolLoadEnd(Address pc,
ConstantPoolEntry::Access* access) {
Instr instr = instr_at(pc);
int opcode = instr & kOpcodeMask;
uint32_t opcode = instr & kOpcodeMask;
bool overflowed = false;
if (!(opcode == kLoadIntptrOpcode || opcode == LFD)) return false;
if (!GetRA(instr).is(kConstantPoolRegister)) {
......
src/ppc/assembler-ppc.cc
View file @ c605ea03
......@@ -355,7 +355,7 @@ bool Assembler::Is32BitLoadIntoR12(Instr instr1, Instr instr2) {
bool Assembler::IsCmpRegister(Instr instr) {
return (((instr & kOpcodeMask) == EXT2) &&
((instr & kExt2OpcodeMask) == CMP));
((EXT2 | (instr & kExt2OpcodeMask)) == CMP));
}
......@@ -370,7 +370,7 @@ bool Assembler::IsAndi(Instr instr) { return ((instr & kOpcodeMask) == ANDIx); }
#if V8_TARGET_ARCH_PPC64
bool Assembler::IsRldicl(Instr instr) {
return (((instr & kOpcodeMask) == EXT5) &&
((instr & kExt5OpcodeMask) == RLDICL));
((EXT5 | (instr & kExt5OpcodeMask)) == RLDICL));
}
#endif
......@@ -382,7 +382,7 @@ bool Assembler::IsCmpImmediate(Instr instr) {
bool Assembler::IsCrSet(Instr instr) {
return (((instr & kOpcodeMask) == EXT1) &&
((instr & kExt1OpcodeMask) == CREQV));
((EXT1 | (instr & kExt1OpcodeMask)) == CREQV));
}
......@@ -425,7 +425,7 @@ enum {
int Assembler::target_at(int pos) {
Instr instr = instr_at(pos);
// check which type of branch this is 16 or 26 bit offset
int opcode = instr & kOpcodeMask;
uint32_t opcode = instr & kOpcodeMask;
int link;
switch (opcode) {
case BX:
......@@ -455,7 +455,7 @@ int Assembler::target_at(int pos) {
void Assembler::target_at_put(int pos, int target_pos, bool* is_branch) {
Instr instr = instr_at(pos);
int opcode = instr & kOpcodeMask;
uint32_t opcode = instr & kOpcodeMask;
if (is_branch != nullptr) {
*is_branch = (opcode == BX || opcode == BCX);
......@@ -535,7 +535,7 @@ void Assembler::target_at_put(int pos, int target_pos, bool* is_branch) {
int Assembler::max_reach_from(int pos) {
Instr instr = instr_at(pos);
int opcode = instr & kOpcodeMask;
uint32_t opcode = instr & kOpcodeMask;
// check which type of branch this is 16 or 26 bit offset
switch (opcode) {
......@@ -646,7 +646,6 @@ void Assembler::x_form(Instr instr, Register ra, Register rs, Register rb,
emit(instr | rs.code() * B21 | ra.code() * B16 | rb.code() * B11 | r);
}
void Assembler::xo_form(Instr instr, Register rt, Register ra, Register rb,
OEBit o, RCBit r) {
emit(instr | rt.code() * B21 | ra.code() * B16 | rb.code() * B11 | o | r);
......@@ -2251,13 +2250,13 @@ void Assembler::fcfidu(const DoubleRegister frt, const DoubleRegister frb,
void Assembler::fcfidus(const DoubleRegister frt, const DoubleRegister frb,
RCBit rc) {
emit(EXT3 | FCFIDU | frt.code() * B21 | frb.code() * B11 | rc);
emit(EXT3 | FCFIDUS | frt.code() * B21 | frb.code() * B11 | rc);
}
void Assembler::fcfids(const DoubleRegister frt, const DoubleRegister frb,
RCBit rc) {
emit(EXT3 | FCFID | frt.code() * B21 | frb.code() * B11 | rc);
emit(EXT3 | FCFIDS | frt.code() * B21 | frb.code() * B11 | rc);
}
......
src/ppc/constants-ppc.h
View file @ c605ea03
This source diff could not be displayed because it is too large. You can view the blob instead.
src/ppc/disasm-ppc.cc
View file @ c605ea03
......@@ -371,13 +371,13 @@ void Decoder::UnknownFormat(Instruction* instr, const char* name) {
void Decoder::DecodeExt1(Instruction* instr) {
switch (instr->Bits(10, 1) << 1) {
switch (EXT1 | (instr->BitField(10, 1))) {
case MCRF: {
UnknownFormat(instr, "mcrf"); // not used by V8
break;
}
case BCLRX: {
int bo = instr->Bits(25, 21) << 21;
int bo = instr->BitField(25, 21);
int bi = instr->Bits(20, 16);
CRBit cond = static_cast<CRBit>(bi & (CRWIDTH - 1));
switch (bo) {
......@@ -447,7 +447,7 @@ void Decoder::DecodeExt1(Instruction* instr) {
break;
}
case BCCTRX: {
switch (instr->Bits(25, 21) << 21) {
switch (instr->BitField(25, 21)) {
case DCBNZF: {
UnknownFormat(instr, "bcctrx-dcbnzf");
break;
......@@ -541,7 +541,7 @@ void Decoder::DecodeExt1(Instruction* instr) {
void Decoder::DecodeExt2(Instruction* instr) {
// Some encodings are 10-1 bits, handle those first
switch (instr->Bits(10, 1) << 1) {
switch (EXT2 | (instr->BitField(10, 1))) {
case SRWX: {
Format(instr, "srw'. 'ra, 'rs, 'rb");
return;
......@@ -642,7 +642,7 @@ void Decoder::DecodeExt2(Instruction* instr) {
#endif
}
switch (instr->Bits(10, 2) << 2) {
switch (EXT2 | (instr->BitField(10, 2))) {
case SRADIX: {
Format(instr, "sradi'. 'ra,'rs,'sh");
return;
......@@ -650,7 +650,7 @@ void Decoder::DecodeExt2(Instruction* instr) {
}
// ?? are all of these xo_form?
switch (instr->Bits(9, 1) << 1) {
switch (EXT2 | (instr->BitField(9, 1))) {
case CMP: {
#if V8_TARGET_ARCH_PPC64
if (instr->Bit(21)) {
......@@ -899,7 +899,7 @@ void Decoder::DecodeExt2(Instruction* instr) {
#endif
}
switch (instr->Bits(5, 1) << 1) {
switch (EXT2 | (instr->BitField(5, 1))) {
case ISEL: {
Format(instr, "isel 'rt, 'ra, 'rb");
return;
......@@ -912,7 +912,7 @@ void Decoder::DecodeExt2(Instruction* instr) {
void Decoder::DecodeExt3(Instruction* instr) {
switch (instr->Bits(10, 1) << 1) {
switch (EXT3 | (instr->BitField(10, 1))) {
case FCFID: {
Format(instr, "fcfids'. 'Dt, 'Db");
break;
......@@ -929,7 +929,7 @@ void Decoder::DecodeExt3(Instruction* instr) {
void Decoder::DecodeExt4(Instruction* instr) {
switch (instr->Bits(5, 1) << 1) {
switch (EXT4 | (instr->BitField(5, 1))) {
case FDIV: {
Format(instr, "fdiv'. 'Dt, 'Da, 'Db");
return;
......@@ -964,7 +964,7 @@ void Decoder::DecodeExt4(Instruction* instr) {
}
}
switch (instr->Bits(10, 1) << 1) {
switch (EXT4 | (instr->BitField(10, 1))) {
case FCMPU: {
Format(instr, "fcmpu 'Da, 'Db");
break;
......@@ -1065,7 +1065,7 @@ void Decoder::DecodeExt4(Instruction* instr) {
void Decoder::DecodeExt5(Instruction* instr) {
switch (instr->Bits(4, 2) << 2) {
switch (EXT5 | (instr->BitField(4, 2))) {
case RLDICL: {
Format(instr, "rldicl'. 'ra, 'rs, 'sh, 'mb");
return;
......@@ -1083,7 +1083,7 @@ void Decoder::DecodeExt5(Instruction* instr) {
return;
}
}
switch (instr->Bits(4, 1) << 1) {
switch (EXT5 | (instr->BitField(4, 1))) {
case RLDCL: {
Format(instr, "rldcl'. 'ra, 'rs, 'sb, 'mb");
return;
......@@ -1093,22 +1093,22 @@ void Decoder::DecodeExt5(Instruction* instr) {
}
void Decoder::DecodeExt6(Instruction* instr) {
switch (instr->Bits(10, 3) << 3) {
switch (EXT6 | (instr->BitField(10, 3))) {
#define DECODE_XX3_INSTRUCTIONS(name, opcode_name, opcode_value) \
case opcode_name: { \
Format(instr, #name" 'Dt, 'Da, 'Db"); \
return; \
}
XX3_OPCODE_LIST(DECODE_XX3_INSTRUCTIONS)
PPC_XX3_OPCODE_LIST(DECODE_XX3_INSTRUCTIONS)
#undef DECODE_XX3_INSTRUCTIONS
}
switch (instr->Bits(10, 2) << 2) {
switch (EXT6 | (instr->BitField(10, 2))) {
#define DECODE_XX2_INSTRUCTIONS(name, opcode_name, opcode_value) \
case opcode_name: { \
Format(instr, #name" 'Dt, 'Db"); \
return; \
}
XX2_OPCODE_LIST(DECODE_XX2_INSTRUCTIONS)
PPC_XX2_OPCODE_LIST(DECODE_XX2_INSTRUCTIONS)
}
#undef DECODE_XX3_INSTRUCTIONS
Unknown(instr); // not used by V8
......@@ -1130,7 +1130,8 @@ int Decoder::InstructionDecode(byte* instr_ptr) {
return Instruction::kInstrSize;
}
switch (instr->OpcodeValue() << 26) {
uint32_t opcode = instr->OpcodeValue() << 26;
switch (opcode) {
case TWI: {
PrintSoftwareInterrupt(instr->SvcValue());
break;
......
src/ppc/simulator-ppc.cc
View file @ c605ea03
......@@ -1623,7 +1623,8 @@ void Simulator::ExecuteBranchConditional(Instruction* instr, BCType type) {
// Handle execution based on instruction types.
void Simulator::ExecuteExt1(Instruction* instr) {
switch (instr->Bits(10, 1) << 1) {
uint32_t opcode = EXT1 | instr->BitField(10, 1);
switch (opcode) {
case MCRF:
UNIMPLEMENTED(); // Not used by V8.
case BCLRX:
......@@ -1678,7 +1679,7 @@ void Simulator::ExecuteExt1(Instruction* instr) {
bool Simulator::ExecuteExt2_10bit(Instruction* instr) {
bool found = true;
int opcode = instr->Bits(10, 1) << 1;
uint32_t opcode = EXT2 | instr->BitField(10, 1);
switch (opcode) {
case SRWX: {
int rs = instr->RSValue();
......@@ -1949,7 +1950,7 @@ bool Simulator::ExecuteExt2_10bit(Instruction* instr) {
if (found) return found;
found = true;
opcode = instr->Bits(10, 2) << 2;
opcode = EXT2 | instr->BitField(10, 2);
switch (opcode) {
case SRADIX: {
int ra = instr->RAValue();
......@@ -1976,7 +1977,7 @@ bool Simulator::ExecuteExt2_10bit(Instruction* instr) {
bool Simulator::ExecuteExt2_9bit_part1(Instruction* instr) {
bool found = true;
int opcode = instr->Bits(9, 1) << 1;
uint32_t opcode = EXT2 | instr->BitField(9, 1);
switch (opcode) {
case TW: {
// used for call redirection in simulation mode
......@@ -2234,7 +2235,7 @@ bool Simulator::ExecuteExt2_9bit_part1(Instruction* instr) {
bool Simulator::ExecuteExt2_9bit_part2(Instruction* instr) {
bool found = true;
int opcode = instr->Bits(9, 1) << 1;
uint32_t opcode = EXT2 | instr->BitField(9, 1);
switch (opcode) {
case CNTLZWX: {
int rs = instr->RSValue();
......@@ -2752,7 +2753,7 @@ bool Simulator::ExecuteExt2_9bit_part2(Instruction* instr) {
void Simulator::ExecuteExt2_5bit(Instruction* instr) {
int opcode = instr->Bits(5, 1) << 1;
uint32_t opcode = EXT2 | instr->BitField(5, 1);
switch (opcode) {
case ISEL: {
int rt = instr->RTValue();
......@@ -2785,9 +2786,9 @@ void Simulator::ExecuteExt2(Instruction* instr) {
void Simulator::ExecuteExt3(Instruction* instr) {
int opcode = instr->Bits(10, 1) << 1;
uint32_t opcode = EXT3 | instr->BitField(10, 1);
switch (opcode) {
case FCFID: {
case FCFIDS: {
// fcfids
int frt = instr->RTValue();
int frb = instr->RBValue();
......@@ -2796,7 +2797,7 @@ void Simulator::ExecuteExt3(Instruction* instr) {
set_d_register_from_double(frt, frt_val);
return;
}
case FCFIDU: {
case FCFIDUS: {
// fcfidus
int frt = instr->RTValue();
int frb = instr->RBValue();
......@@ -2811,7 +2812,8 @@ void Simulator::ExecuteExt3(Instruction* instr) {
void Simulator::ExecuteExt4(Instruction* instr) {
switch (instr->Bits(5, 1) << 1) {
uint32_t opcode = EXT4 | instr->BitField(5, 1);
switch (opcode) {
case FDIV: {
int frt = instr->RTValue();
int fra = instr->RAValue();
......@@ -2898,7 +2900,7 @@ void Simulator::ExecuteExt4(Instruction* instr) {
return;
}
}
int opcode = instr->Bits(10, 1) << 1;
opcode = EXT4 | instr->BitField(10, 1);
switch (opcode) {
case FCMPU: {
int fra = instr->RAValue();
......@@ -3236,7 +3238,8 @@ void Simulator::ExecuteExt4(Instruction* instr) {
#if V8_TARGET_ARCH_PPC64
void Simulator::ExecuteExt5(Instruction* instr) {
switch (instr->Bits(4, 2) << 2) {
uint32_t opcode = EXT5 | instr->BitField(4, 2);
switch (opcode) {
case RLDICL: {
int ra = instr->RAValue();
int rs = instr->RSValue();
......@@ -3324,7 +3327,8 @@ void Simulator::ExecuteExt5(Instruction* instr) {
return;
}
}
switch (instr->Bits(4, 1) << 1) {
opcode = EXT5 | instr->BitField(4, 1);
switch (opcode) {
case RLDCL: {
int ra = instr->RAValue();
int rs = instr->RSValue();
......@@ -3350,7 +3354,8 @@ void Simulator::ExecuteExt5(Instruction* instr) {
#endif
void Simulator::ExecuteExt6(Instruction* instr) {
switch (instr->Bits(10, 3) << 3) {
uint32_t opcode = EXT6 | instr->BitField(10, 3);
switch (opcode) {
case XSADDDP: {
int frt = instr->RTValue();
int fra = instr->RAValue();
......@@ -3396,7 +3401,7 @@ void Simulator::ExecuteExt6(Instruction* instr) {
}
void Simulator::ExecuteGeneric(Instruction* instr) {
int opcode = instr->OpcodeValue() << 26;
uint32_t opcode = instr->OpcodeField();
switch (opcode) {
case SUBFIC: {
int rt = instr->RTValue();
......@@ -3963,7 +3968,7 @@ void Simulator::ExecuteInstruction(Instruction* instr) {
if (::v8::internal::FLAG_trace_sim) {
Trace(instr);
}
int opcode = instr->OpcodeValue() << 26;
uint32_t opcode = instr->OpcodeField();
if (opcode == TWI) {
SoftwareInterrupt(instr);
} else {
......
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