PPC: [wasm-simd] Prototype extended pairwise addition

Bug: v8:11086
Change-Id: Ib896020b0865c0f87cabbde254bc8af36ce705d3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2623007Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#72020}

src/codegen/ppc/constants-ppc.h

@@ -2273,14 +2273,22 @@ using Instr = uint32_t;
   V(vmuluwm, VMULUWM, 0x10000089)                          \
   /* Vector Pack Unsigned Halfword Unsigned Modulo */      \
   V(vpkuhum, VPKUHUM, 0x1000000E)                          \
+  /* Vector Multiply Even Signed Byte */                   \
+  V(vmulesb, VMULESB, 0x10000308)                          \
   /* Vector Multiply Even Unsigned Byte */                 \
   V(vmuleub, VMULEUB, 0x10000208)                          \
+  /* Vector Multiply Odd Signed Byte */                    \
+  V(vmulosb, VMULOSB, 0x10000108)                          \
   /* Vector Multiply Odd Unsigned Byte */                  \
   V(vmuloub, VMULOUB, 0x10000008)                          \
   /* Vector Multiply Even Unsigned Halfword */             \
   V(vmuleuh, VMULEUH, 0x10000248)                          \
+  /* Vector Multiply Even Signed Halfword */               \
+  V(vmulesh, VMULESH, 0x10000348)                          \
   /* Vector Multiply Odd Unsigned Halfword */              \
   V(vmulouh, VMULOUH, 0x10000048)                          \
+  /* Vector Multiply Odd Signed Halfword */                \
+  V(vmulosh, VMULOSH, 0x10000148)                          \
   /* Vector Sum across Quarter Signed Halfword Saturate */ \
   V(vsum4shs, VSUM4SHS, 0x10000648)                        \
   /* Vector Pack Unsigned Word Unsigned Saturate */        \
@@ -2461,18 +2469,10 @@ using Instr = uint32_t;
   V(vmrglh, VMRGLH, 0x1000014C)                                           \
   /* Vector Merge Low Word */                                             \
   V(vmrglw, VMRGLW, 0x1000018C)                                           \
-  /* Vector Multiply Even Signed Byte */                                  \
-  V(vmulesb, VMULESB, 0x10000308)                                         \
-  /* Vector Multiply Even Signed Halfword */                              \
-  V(vmulesh, VMULESH, 0x10000348)                                         \
   /* Vector Multiply Even Signed Word */                                  \
   V(vmulesw, VMULESW, 0x10000388)                                         \
   /* Vector Multiply Even Unsigned Word */                                \
   V(vmuleuw, VMULEUW, 0x10000288)                                         \
-  /* Vector Multiply Odd Signed Byte */                                   \
-  V(vmulosb, VMULOSB, 0x10000108)                                         \
-  /* Vector Multiply Odd Signed Halfword */                               \
-  V(vmulosh, VMULOSH, 0x10000148)                                         \
   /* Vector Multiply Odd Signed Word */                                   \
   V(vmulosw, VMULOSW, 0x10000188)                                         \
   /* Vector Multiply Odd Unsigned Word */                                 \

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -3672,6 +3672,48 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ stxsdx(kScratchSimd128Reg, operand);
       break;
     }
+#define EXT_ADD_PAIRWISE(mul_even, mul_odd, add)           \
+  __ mul_even(tempFPReg1, src, kScratchSimd128Reg);        \
+  __ mul_odd(kScratchSimd128Reg, src, kScratchSimd128Reg); \
+  __ add(dst, tempFPReg1, kScratchSimd128Reg);
+    case kPPC_I32x4ExtAddPairwiseI16x8S: {
+      Simd128Register src = i.InputSimd128Register(0);
+      Simd128Register dst = i.OutputSimd128Register();
+      Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
+      __ li(kScratchReg, Operand(1));
+      __ mtvsrd(kScratchSimd128Reg, kScratchReg);
+      __ vsplth(kScratchSimd128Reg, kScratchSimd128Reg, Operand(3));
+      EXT_ADD_PAIRWISE(vmulesh, vmulesh, vadduwm)
+      break;
+    }
+    case kPPC_I32x4ExtAddPairwiseI16x8U: {
+      Simd128Register src = i.InputSimd128Register(0);
+      Simd128Register dst = i.OutputSimd128Register();
+      Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
+      __ li(kScratchReg, Operand(1));
+      __ mtvsrd(kScratchSimd128Reg, kScratchReg);
+      __ vsplth(kScratchSimd128Reg, kScratchSimd128Reg, Operand(3));
+      EXT_ADD_PAIRWISE(vmuleuh, vmuleuh, vadduwm)
+      break;
+    }
+
+    case kPPC_I16x8ExtAddPairwiseI8x16S: {
+      Simd128Register src = i.InputSimd128Register(0);
+      Simd128Register dst = i.OutputSimd128Register();
+      Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
+      __ xxspltib(kScratchSimd128Reg, Operand(1));
+      EXT_ADD_PAIRWISE(vmulesb, vmulesb, vadduhm)
+      break;
+    }
+    case kPPC_I16x8ExtAddPairwiseI8x16U: {
+      Simd128Register src = i.InputSimd128Register(0);
+      Simd128Register dst = i.OutputSimd128Register();
+      Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
+      __ xxspltib(kScratchSimd128Reg, Operand(1));
+      EXT_ADD_PAIRWISE(vmuleub, vmuleub, vadduhm)
+      break;
+    }
+#undef EXT_ADD_PAIRWISE
     case kPPC_StoreCompressTagged: {
       ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
       break;

src/compiler/backend/ppc/instruction-codes-ppc.h

@@ -294,6 +294,8 @@ namespace compiler {
   V(PPC_I32x4UConvertI16x8High)      \
   V(PPC_I32x4BitMask)                \
   V(PPC_I32x4DotI16x8S)              \
+  V(PPC_I32x4ExtAddPairwiseI16x8S)   \
+  V(PPC_I32x4ExtAddPairwiseI16x8U)   \
   V(PPC_F32x4Qfma)                   \
   V(PPC_F32x4Qfms)                   \
   V(PPC_I16x8Splat)                  \
@@ -331,6 +333,8 @@ namespace compiler {
   V(PPC_I16x8SubSatU)                \
   V(PPC_I16x8RoundingAverageU)       \
   V(PPC_I16x8BitMask)                \
+  V(PPC_I16x8ExtAddPairwiseI8x16S)   \
+  V(PPC_I16x8ExtAddPairwiseI8x16U)   \
   V(PPC_I8x16Splat)                  \
   V(PPC_I8x16ExtractLaneU)           \
   V(PPC_I8x16ExtractLaneS)           \

src/compiler/backend/ppc/instruction-scheduler-ppc.cc

@@ -219,6 +219,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_I32x4UConvertI16x8High:
     case kPPC_I32x4BitMask:
     case kPPC_I32x4DotI16x8S:
+    case kPPC_I32x4ExtAddPairwiseI16x8S:
+    case kPPC_I32x4ExtAddPairwiseI16x8U:
     case kPPC_I16x8Splat:
     case kPPC_I16x8ExtractLaneU:
     case kPPC_I16x8ExtractLaneS:
@@ -254,6 +256,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_I16x8SubSatU:
     case kPPC_I16x8RoundingAverageU:
     case kPPC_I16x8BitMask:
+    case kPPC_I16x8ExtAddPairwiseI8x16S:
+    case kPPC_I16x8ExtAddPairwiseI8x16U:
     case kPPC_I8x16Splat:
     case kPPC_I8x16ExtractLaneU:
     case kPPC_I8x16ExtractLaneS: