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Commit c1eaae64 authored by Clemens Hammacher's avatar Clemens Hammacher Committed by Commit Bot
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[Assembler][ia32] Pass Operand by value 

The Operand class is small enough to be efficiently passed by value.
This saves binary size and performance because the Operand does not need
to be emitted to the caller's frame and loaded in the callee.
Binary saving is 37kB in release mode on ia32.

R=mstarzinger@chromium.org

Bug: v8:7310
Change-Id: Ibc103622ec216725c762c2ba4bb96451c99db556
Reviewed-on: https://chromium-review.googlesource.com/934264
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Reviewed-by: 's avatarMichael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#51555}
parent bd720499
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Showing with 511 additions and 656 deletions
src/assembler.h
View file @ c1eaae64
......@@ -358,7 +358,7 @@ class RelocInfo {
// The maximum pc delta that will use the short encoding.
static const int kMaxSmallPCDelta;
enum Mode {
enum Mode : int8_t {
// Please note the order is important (see IsCodeTarget, IsGCRelocMode).
CODE_TARGET,
EMBEDDED_OBJECT,
......
src/compiler/common-operator.cc
View file @ c1eaae64
......@@ -220,7 +220,7 @@ bool operator!=(RelocatablePtrConstantInfo const& lhs,
}
size_t hash_value(RelocatablePtrConstantInfo const& p) {
return base::hash_combine(p.value(), p.rmode(), p.type());
return base::hash_combine(p.value(), int8_t{p.rmode()}, p.type());
}
std::ostream& operator<<(std::ostream& os,
......
src/ia32/assembler-ia32.cc
View file @ c1eaae64
......@@ -533,8 +533,7 @@ void Assembler::push(Register src) {
EMIT(0x50 | src.code());
}
void Assembler::push(const Operand& src) {
void Assembler::push(Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xFF);
emit_operand(esi, src);
......@@ -547,8 +546,7 @@ void Assembler::pop(Register dst) {
EMIT(0x58 | dst.code());
}
void Assembler::pop(const Operand& dst) {
void Assembler::pop(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0x8F);
emit_operand(eax, dst);
......@@ -568,48 +566,42 @@ void Assembler::leave() {
EMIT(0xC9);
}
void Assembler::mov_b(Register dst, const Operand& src) {
void Assembler::mov_b(Register dst, Operand src) {
CHECK(dst.is_byte_register());
EnsureSpace ensure_space(this);
EMIT(0x8A);
emit_operand(dst, src);
}
void Assembler::mov_b(const Operand& dst, const Immediate& src) {
void Assembler::mov_b(Operand dst, const Immediate& src) {
EnsureSpace ensure_space(this);
EMIT(0xC6);
emit_operand(eax, dst);
EMIT(static_cast<int8_t>(src.immediate()));
}
void Assembler::mov_b(const Operand& dst, Register src) {
void Assembler::mov_b(Operand dst, Register src) {
CHECK(src.is_byte_register());
EnsureSpace ensure_space(this);
EMIT(0x88);
emit_operand(src, dst);
}
void Assembler::mov_w(Register dst, const Operand& src) {
void Assembler::mov_w(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x8B);
emit_operand(dst, src);
}
void Assembler::mov_w(const Operand& dst, Register src) {
void Assembler::mov_w(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x89);
emit_operand(src, dst);
}
void Assembler::mov_w(const Operand& dst, const Immediate& src) {
void Assembler::mov_w(Operand dst, const Immediate& src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0xC7);
......@@ -638,8 +630,7 @@ void Assembler::mov(Register dst, Handle<HeapObject> handle) {
emit(handle);
}
void Assembler::mov(Register dst, const Operand& src) {
void Assembler::mov(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x8B);
emit_operand(dst, src);
......@@ -652,69 +643,62 @@ void Assembler::mov(Register dst, Register src) {
EMIT(0xC0 | src.code() << 3 | dst.code());
}
void Assembler::mov(const Operand& dst, const Immediate& x) {
void Assembler::mov(Operand dst, const Immediate& x) {
EnsureSpace ensure_space(this);
EMIT(0xC7);
emit_operand(eax, dst);
emit(x);
}
void Assembler::mov(const Operand& dst, Address src, RelocInfo::Mode rmode) {
void Assembler::mov(Operand dst, Address src, RelocInfo::Mode rmode) {
EnsureSpace ensure_space(this);
EMIT(0xC7);
emit_operand(eax, dst);
emit(reinterpret_cast<uint32_t>(src), rmode);
}
void Assembler::mov(const Operand& dst, Handle<HeapObject> handle) {
void Assembler::mov(Operand dst, Handle<HeapObject> handle) {
EnsureSpace ensure_space(this);
EMIT(0xC7);
emit_operand(eax, dst);
emit(handle);
}
void Assembler::mov(const Operand& dst, Register src) {
void Assembler::mov(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x89);
emit_operand(src, dst);
}
void Assembler::movsx_b(Register dst, const Operand& src) {
void Assembler::movsx_b(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xBE);
emit_operand(dst, src);
}
void Assembler::movsx_w(Register dst, const Operand& src) {
void Assembler::movsx_w(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xBF);
emit_operand(dst, src);
}
void Assembler::movzx_b(Register dst, const Operand& src) {
void Assembler::movzx_b(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xB6);
emit_operand(dst, src);
}
void Assembler::movzx_w(Register dst, const Operand& src) {
void Assembler::movzx_w(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xB7);
emit_operand(dst, src);
}
void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
void Assembler::cmov(Condition cc, Register dst, Operand src) {
EnsureSpace ensure_space(this);
// Opcode: 0f 40 + cc /r.
EMIT(0x0F);
......@@ -759,21 +743,20 @@ void Assembler::xchg(Register dst, Register src) {
}
}
void Assembler::xchg(Register dst, const Operand& src) {
void Assembler::xchg(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x87);
emit_operand(dst, src);
}
void Assembler::xchg_b(Register reg, const Operand& op) {
void Assembler::xchg_b(Register reg, Operand op) {
DCHECK(reg.is_byte_register());
EnsureSpace ensure_space(this);
EMIT(0x86);
emit_operand(reg, op);
}
void Assembler::xchg_w(Register reg, const Operand& op) {
void Assembler::xchg_w(Register reg, Operand op) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x87);
......@@ -785,14 +768,14 @@ void Assembler::lock() {
EMIT(0xF0);
}
void Assembler::cmpxchg(const Operand& dst, Register src) {
void Assembler::cmpxchg(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xB1);
emit_operand(src, dst);
}
void Assembler::cmpxchg_b(const Operand& dst, Register src) {
void Assembler::cmpxchg_b(Operand dst, Register src) {
DCHECK(src.is_byte_register());
EnsureSpace ensure_space(this);
EMIT(0x0F);
......@@ -800,7 +783,7 @@ void Assembler::cmpxchg_b(const Operand& dst, Register src) {
emit_operand(src, dst);
}
void Assembler::cmpxchg_w(const Operand& dst, Register src) {
void Assembler::cmpxchg_w(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -826,29 +809,25 @@ void Assembler::adc(Register dst, int32_t imm32) {
emit_arith(2, Operand(dst), Immediate(imm32));
}
void Assembler::adc(Register dst, const Operand& src) {
void Assembler::adc(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x13);
emit_operand(dst, src);
}
void Assembler::add(Register dst, const Operand& src) {
void Assembler::add(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x03);
emit_operand(dst, src);
}
void Assembler::add(const Operand& dst, Register src) {
void Assembler::add(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x01);
emit_operand(src, dst);
}
void Assembler::add(const Operand& dst, const Immediate& x) {
void Assembler::add(Operand dst, const Immediate& x) {
DCHECK_NOT_NULL(reloc_info_writer.last_pc());
EnsureSpace ensure_space(this);
emit_arith(0, dst, x);
......@@ -865,27 +844,24 @@ void Assembler::and_(Register dst, const Immediate& x) {
emit_arith(4, Operand(dst), x);
}
void Assembler::and_(Register dst, const Operand& src) {
void Assembler::and_(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x23);
emit_operand(dst, src);
}
void Assembler::and_(const Operand& dst, const Immediate& x) {
void Assembler::and_(Operand dst, const Immediate& x) {
EnsureSpace ensure_space(this);
emit_arith(4, dst, x);
}
void Assembler::and_(const Operand& dst, Register src) {
void Assembler::and_(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x21);
emit_operand(src, dst);
}
void Assembler::cmpb(const Operand& op, Immediate imm8) {
void Assembler::cmpb(Operand op, Immediate imm8) {
DCHECK(imm8.is_int8() || imm8.is_uint8());
EnsureSpace ensure_space(this);
if (op.is_reg(eax)) {
......@@ -897,24 +873,21 @@ void Assembler::cmpb(const Operand& op, Immediate imm8) {
emit_b(imm8);
}
void Assembler::cmpb(const Operand& op, Register reg) {
void Assembler::cmpb(Operand op, Register reg) {
CHECK(reg.is_byte_register());
EnsureSpace ensure_space(this);
EMIT(0x38);
emit_operand(reg, op);
}
void Assembler::cmpb(Register reg, const Operand& op) {
void Assembler::cmpb(Register reg, Operand op) {
CHECK(reg.is_byte_register());
EnsureSpace ensure_space(this);
EMIT(0x3A);
emit_operand(reg, op);
}
void Assembler::cmpw(const Operand& op, Immediate imm16) {
void Assembler::cmpw(Operand op, Immediate imm16) {
DCHECK(imm16.is_int16() || imm16.is_uint16());
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -923,14 +896,14 @@ void Assembler::cmpw(const Operand& op, Immediate imm16) {
emit_w(imm16);
}
void Assembler::cmpw(Register reg, const Operand& op) {
void Assembler::cmpw(Register reg, Operand op) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x3B);
emit_operand(reg, op);
}
void Assembler::cmpw(const Operand& op, Register reg) {
void Assembler::cmpw(Operand op, Register reg) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x39);
......@@ -947,38 +920,35 @@ void Assembler::cmp(Register reg, Handle<HeapObject> handle) {
emit_arith(7, Operand(reg), Immediate(handle));
}
void Assembler::cmp(Register reg, const Operand& op) {
void Assembler::cmp(Register reg, Operand op) {
EnsureSpace ensure_space(this);
EMIT(0x3B);
emit_operand(reg, op);
}
void Assembler::cmp(const Operand& op, Register reg) {
void Assembler::cmp(Operand op, Register reg) {
EnsureSpace ensure_space(this);
EMIT(0x39);
emit_operand(reg, op);
}
void Assembler::cmp(const Operand& op, const Immediate& imm) {
void Assembler::cmp(Operand op, const Immediate& imm) {
EnsureSpace ensure_space(this);
emit_arith(7, op, imm);
}
void Assembler::cmp(const Operand& op, Handle<HeapObject> handle) {
void Assembler::cmp(Operand op, Handle<HeapObject> handle) {
EnsureSpace ensure_space(this);
emit_arith(7, op, Immediate(handle));
}
void Assembler::cmpb_al(const Operand& op) {
void Assembler::cmpb_al(Operand op) {
EnsureSpace ensure_space(this);
EMIT(0x38); // CMP r/m8, r8
emit_operand(eax, op); // eax has same code as register al.
}
void Assembler::cmpw_ax(const Operand& op) {
void Assembler::cmpw_ax(Operand op) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x39); // CMP r/m16, r16
......@@ -993,8 +963,7 @@ void Assembler::dec_b(Register dst) {
EMIT(0xC8 | dst.code());
}
void Assembler::dec_b(const Operand& dst) {
void Assembler::dec_b(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xFE);
emit_operand(ecx, dst);
......@@ -1006,8 +975,7 @@ void Assembler::dec(Register dst) {
EMIT(0x48 | dst.code());
}
void Assembler::dec(const Operand& dst) {
void Assembler::dec(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xFF);
emit_operand(ecx, dst);
......@@ -1019,15 +987,13 @@ void Assembler::cdq() {
EMIT(0x99);
}
void Assembler::idiv(const Operand& src) {
void Assembler::idiv(Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF7);
emit_operand(edi, src);
}
void Assembler::div(const Operand& src) {
void Assembler::div(Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF7);
emit_operand(esi, src);
......@@ -1040,8 +1006,7 @@ void Assembler::imul(Register reg) {
EMIT(0xE8 | reg.code());
}
void Assembler::imul(Register dst, const Operand& src) {
void Assembler::imul(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xAF);
......@@ -1053,8 +1018,7 @@ void Assembler::imul(Register dst, Register src, int32_t imm32) {
imul(dst, Operand(src), imm32);
}
void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
void Assembler::imul(Register dst, Operand src, int32_t imm32) {
EnsureSpace ensure_space(this);
if (is_int8(imm32)) {
EMIT(0x6B);
......@@ -1073,15 +1037,13 @@ void Assembler::inc(Register dst) {
EMIT(0x40 | dst.code());
}
void Assembler::inc(const Operand& dst) {
void Assembler::inc(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xFF);
emit_operand(eax, dst);
}
void Assembler::lea(Register dst, const Operand& src) {
void Assembler::lea(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x8D);
emit_operand(dst, src);
......@@ -1101,8 +1063,7 @@ void Assembler::neg(Register dst) {
EMIT(0xD8 | dst.code());
}
void Assembler::neg(const Operand& dst) {
void Assembler::neg(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xF7);
emit_operand(ebx, dst);
......@@ -1115,8 +1076,7 @@ void Assembler::not_(Register dst) {
EMIT(0xD0 | dst.code());
}
void Assembler::not_(const Operand& dst) {
void Assembler::not_(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xF7);
emit_operand(edx, dst);
......@@ -1128,21 +1088,18 @@ void Assembler::or_(Register dst, int32_t imm32) {
emit_arith(1, Operand(dst), Immediate(imm32));
}
void Assembler::or_(Register dst, const Operand& src) {
void Assembler::or_(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0B);
emit_operand(dst, src);
}
void Assembler::or_(const Operand& dst, const Immediate& x) {
void Assembler::or_(Operand dst, const Immediate& x) {
EnsureSpace ensure_space(this);
emit_arith(1, dst, x);
}
void Assembler::or_(const Operand& dst, Register src) {
void Assembler::or_(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x09);
emit_operand(src, dst);
......@@ -1176,8 +1133,7 @@ void Assembler::rcr(Register dst, uint8_t imm8) {
}
}
void Assembler::ror(const Operand& dst, uint8_t imm8) {
void Assembler::ror(Operand dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
......@@ -1190,15 +1146,13 @@ void Assembler::ror(const Operand& dst, uint8_t imm8) {
}
}
void Assembler::ror_cl(const Operand& dst) {
void Assembler::ror_cl(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
emit_operand(ecx, dst);
}
void Assembler::sar(const Operand& dst, uint8_t imm8) {
void Assembler::sar(Operand dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
......@@ -1211,14 +1165,13 @@ void Assembler::sar(const Operand& dst, uint8_t imm8) {
}
}
void Assembler::sar_cl(const Operand& dst) {
void Assembler::sar_cl(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
emit_operand(edi, dst);
}
void Assembler::sbb(Register dst, const Operand& src) {
void Assembler::sbb(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x1B);
emit_operand(dst, src);
......@@ -1240,8 +1193,7 @@ void Assembler::shld_cl(Register dst, Register src) {
emit_operand(src, Operand(dst));
}
void Assembler::shl(const Operand& dst, uint8_t imm8) {
void Assembler::shl(Operand dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
......@@ -1254,14 +1206,13 @@ void Assembler::shl(const Operand& dst, uint8_t imm8) {
}
}
void Assembler::shl_cl(const Operand& dst) {
void Assembler::shl_cl(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
emit_operand(esp, dst);
}
void Assembler::shr(const Operand& dst, uint8_t imm8) {
void Assembler::shr(Operand dst, uint8_t imm8) {
EnsureSpace ensure_space(this);
DCHECK(is_uint5(imm8)); // illegal shift count
if (imm8 == 1) {
......@@ -1274,8 +1225,7 @@ void Assembler::shr(const Operand& dst, uint8_t imm8) {
}
}
void Assembler::shr_cl(const Operand& dst) {
void Assembler::shr_cl(Operand dst) {
EnsureSpace ensure_space(this);
EMIT(0xD3);
emit_operand(ebp, dst);
......@@ -1290,27 +1240,25 @@ void Assembler::shrd(Register dst, Register src, uint8_t shift) {
EMIT(shift);
}
void Assembler::shrd_cl(const Operand& dst, Register src) {
void Assembler::shrd_cl(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xAD);
emit_operand(src, dst);
}
void Assembler::sub(const Operand& dst, const Immediate& x) {
void Assembler::sub(Operand dst, const Immediate& x) {
EnsureSpace ensure_space(this);
emit_arith(5, dst, x);
}
void Assembler::sub(Register dst, const Operand& src) {
void Assembler::sub(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x2B);
emit_operand(dst, src);
}
void Assembler::sub(const Operand& dst, Register src) {
void Assembler::sub(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x29);
emit_operand(src, dst);
......@@ -1342,23 +1290,20 @@ void Assembler::test(Register reg, const Immediate& imm) {
emit(imm);
}
void Assembler::test(Register reg, const Operand& op) {
void Assembler::test(Register reg, Operand op) {
EnsureSpace ensure_space(this);
EMIT(0x85);
emit_operand(reg, op);
}
void Assembler::test_b(Register reg, const Operand& op) {
void Assembler::test_b(Register reg, Operand op) {
CHECK(reg.is_byte_register());
EnsureSpace ensure_space(this);
EMIT(0x84);
emit_operand(reg, op);
}
void Assembler::test(const Operand& op, const Immediate& imm) {
void Assembler::test(Operand op, const Immediate& imm) {
if (op.is_reg_only()) {
test(op.reg(), imm);
return;
......@@ -1390,7 +1335,7 @@ void Assembler::test_b(Register reg, Immediate imm8) {
}
}
void Assembler::test_b(const Operand& op, Immediate imm8) {
void Assembler::test_b(Operand op, Immediate imm8) {
if (op.is_reg_only()) {
test_b(op.reg(), imm8);
return;
......@@ -1415,14 +1360,14 @@ void Assembler::test_w(Register reg, Immediate imm16) {
}
}
void Assembler::test_w(Register reg, const Operand& op) {
void Assembler::test_w(Register reg, Operand op) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x85);
emit_operand(reg, op);
}
void Assembler::test_w(const Operand& op, Immediate imm16) {
void Assembler::test_w(Operand op, Immediate imm16) {
DCHECK(imm16.is_int16() || imm16.is_uint16());
if (op.is_reg_only()) {
test_w(op.reg(), imm16);
......@@ -1440,52 +1385,45 @@ void Assembler::xor_(Register dst, int32_t imm32) {
emit_arith(6, Operand(dst), Immediate(imm32));
}
void Assembler::xor_(Register dst, const Operand& src) {
void Assembler::xor_(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x33);
emit_operand(dst, src);
}
void Assembler::xor_(const Operand& dst, Register src) {
void Assembler::xor_(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x31);
emit_operand(src, dst);
}
void Assembler::xor_(const Operand& dst, const Immediate& x) {
void Assembler::xor_(Operand dst, const Immediate& x) {
EnsureSpace ensure_space(this);
emit_arith(6, dst, x);
}
void Assembler::bt(const Operand& dst, Register src) {
void Assembler::bt(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xA3);
emit_operand(src, dst);
}
void Assembler::bts(const Operand& dst, Register src) {
void Assembler::bts(Operand dst, Register src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xAB);
emit_operand(src, dst);
}
void Assembler::bsr(Register dst, const Operand& src) {
void Assembler::bsr(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xBD);
emit_operand(dst, src);
}
void Assembler::bsf(Register dst, const Operand& src) {
void Assembler::bsf(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xBC);
......@@ -1675,13 +1613,12 @@ void Assembler::wasm_call(Address entry, RelocInfo::Mode rmode) {
emit(reinterpret_cast<intptr_t>(entry), rmode);
}
int Assembler::CallSize(const Operand& adr) {
int Assembler::CallSize(Operand adr) {
// Call size is 1 (opcode) + adr.len_ (operand).
return 1 + adr.len_;
}
void Assembler::call(const Operand& adr) {
void Assembler::call(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xFF);
emit_operand(edx, adr);
......@@ -1754,8 +1691,7 @@ void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
}
}
void Assembler::jmp(const Operand& adr) {
void Assembler::jmp(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xFF);
emit_operand(esp, adr);
......@@ -1879,94 +1815,81 @@ void Assembler::fldln2() {
EMIT(0xED);
}
void Assembler::fld_s(const Operand& adr) {
void Assembler::fld_s(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xD9);
emit_operand(eax, adr);
}
void Assembler::fld_d(const Operand& adr) {
void Assembler::fld_d(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDD);
emit_operand(eax, adr);
}
void Assembler::fstp_s(const Operand& adr) {
void Assembler::fstp_s(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xD9);
emit_operand(ebx, adr);
}
void Assembler::fst_s(const Operand& adr) {
void Assembler::fst_s(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xD9);
emit_operand(edx, adr);
}
void Assembler::fstp_d(const Operand& adr) {
void Assembler::fstp_d(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDD);
emit_operand(ebx, adr);
}
void Assembler::fst_d(const Operand& adr) {
void Assembler::fst_d(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDD);
emit_operand(edx, adr);
}
void Assembler::fild_s(const Operand& adr) {
void Assembler::fild_s(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDB);
emit_operand(eax, adr);
}
void Assembler::fild_d(const Operand& adr) {
void Assembler::fild_d(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDF);
emit_operand(ebp, adr);
}
void Assembler::fistp_s(const Operand& adr) {
void Assembler::fistp_s(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDB);
emit_operand(ebx, adr);
}
void Assembler::fisttp_s(const Operand& adr) {
void Assembler::fisttp_s(Operand adr) {
DCHECK(IsEnabled(SSE3));
EnsureSpace ensure_space(this);
EMIT(0xDB);
emit_operand(ecx, adr);
}
void Assembler::fisttp_d(const Operand& adr) {
void Assembler::fisttp_d(Operand adr) {
DCHECK(IsEnabled(SSE3));
EnsureSpace ensure_space(this);
EMIT(0xDD);
emit_operand(ecx, adr);
}
void Assembler::fist_s(const Operand& adr) {
void Assembler::fist_s(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDB);
emit_operand(edx, adr);
}
void Assembler::fistp_d(const Operand& adr) {
void Assembler::fistp_d(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDF);
emit_operand(edi, adr);
......@@ -2059,8 +1982,7 @@ void Assembler::fsub_i(int i) {
emit_farith(0xD8, 0xE0, i);
}
void Assembler::fisub_s(const Operand& adr) {
void Assembler::fisub_s(Operand adr) {
EnsureSpace ensure_space(this);
EMIT(0xDA);
emit_operand(esp, adr);
......@@ -2236,8 +2158,7 @@ void Assembler::setcc(Condition cc, Register reg) {
EMIT(0xC0 | reg.code());
}
void Assembler::cvttss2si(Register dst, const Operand& src) {
void Assembler::cvttss2si(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2245,8 +2166,7 @@ void Assembler::cvttss2si(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::cvttsd2si(Register dst, const Operand& src) {
void Assembler::cvttsd2si(Register dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2263,8 +2183,7 @@ void Assembler::cvtsd2si(Register dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtsi2ss(XMMRegister dst, const Operand& src) {
void Assembler::cvtsi2ss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2272,8 +2191,7 @@ void Assembler::cvtsi2ss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
void Assembler::cvtsi2sd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2281,8 +2199,7 @@ void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
void Assembler::cvtss2sd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2290,8 +2207,7 @@ void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
void Assembler::cvtsd2ss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2299,14 +2215,14 @@ void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::cvtdq2ps(XMMRegister dst, const Operand& src) {
void Assembler::cvtdq2ps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5B);
emit_sse_operand(dst, src);
}
void Assembler::cvttps2dq(XMMRegister dst, const Operand& src) {
void Assembler::cvttps2dq(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2314,7 +2230,7 @@ void Assembler::cvttps2dq(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::addsd(XMMRegister dst, const Operand& src) {
void Assembler::addsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2322,8 +2238,7 @@ void Assembler::addsd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::mulsd(XMMRegister dst, const Operand& src) {
void Assembler::mulsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2331,8 +2246,7 @@ void Assembler::mulsd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::subsd(XMMRegister dst, const Operand& src) {
void Assembler::subsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2340,8 +2254,7 @@ void Assembler::subsd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::divsd(XMMRegister dst, const Operand& src) {
void Assembler::divsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2358,91 +2271,84 @@ void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::andps(XMMRegister dst, const Operand& src) {
void Assembler::andps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x54);
emit_sse_operand(dst, src);
}
void Assembler::orps(XMMRegister dst, const Operand& src) {
void Assembler::orps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x56);
emit_sse_operand(dst, src);
}
void Assembler::xorps(XMMRegister dst, const Operand& src) {
void Assembler::xorps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x57);
emit_sse_operand(dst, src);
}
void Assembler::addps(XMMRegister dst, const Operand& src) {
void Assembler::addps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x58);
emit_sse_operand(dst, src);
}
void Assembler::subps(XMMRegister dst, const Operand& src) {
void Assembler::subps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5C);
emit_sse_operand(dst, src);
}
void Assembler::mulps(XMMRegister dst, const Operand& src) {
void Assembler::mulps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x59);
emit_sse_operand(dst, src);
}
void Assembler::divps(XMMRegister dst, const Operand& src) {
void Assembler::divps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5E);
emit_sse_operand(dst, src);
}
void Assembler::rcpps(XMMRegister dst, const Operand& src) {
void Assembler::rcpps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x53);
emit_sse_operand(dst, src);
}
void Assembler::rsqrtps(XMMRegister dst, const Operand& src) {
void Assembler::rsqrtps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x52);
emit_sse_operand(dst, src);
}
void Assembler::minps(XMMRegister dst, const Operand& src) {
void Assembler::minps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5D);
emit_sse_operand(dst, src);
}
void Assembler::maxps(XMMRegister dst, const Operand& src) {
void Assembler::maxps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x5F);
emit_sse_operand(dst, src);
}
void Assembler::cmpps(XMMRegister dst, const Operand& src, int8_t cmp) {
void Assembler::cmpps(XMMRegister dst, Operand src, int8_t cmp) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xC2);
......@@ -2450,7 +2356,7 @@ void Assembler::cmpps(XMMRegister dst, const Operand& src, int8_t cmp) {
EMIT(cmp);
}
void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
void Assembler::sqrtsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2458,7 +2364,7 @@ void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::haddps(XMMRegister dst, const Operand& src) {
void Assembler::haddps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2483,8 +2389,7 @@ void Assembler::orpd(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
void Assembler::ucomisd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2535,8 +2440,7 @@ void Assembler::movmskps(Register dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::maxsd(XMMRegister dst, const Operand& src) {
void Assembler::maxsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2544,8 +2448,7 @@ void Assembler::maxsd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::minsd(XMMRegister dst, const Operand& src) {
void Assembler::minsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2578,14 +2481,14 @@ void Assembler::movups(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::movups(XMMRegister dst, const Operand& src) {
void Assembler::movups(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x10);
emit_sse_operand(dst, src);
}
void Assembler::movups(const Operand& dst, XMMRegister src) {
void Assembler::movups(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x11);
......@@ -2601,8 +2504,7 @@ void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
EMIT(imm8);
}
void Assembler::movdqa(const Operand& dst, XMMRegister src) {
void Assembler::movdqa(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2610,8 +2512,7 @@ void Assembler::movdqa(const Operand& dst, XMMRegister src) {
emit_sse_operand(src, dst);
}
void Assembler::movdqa(XMMRegister dst, const Operand& src) {
void Assembler::movdqa(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2619,8 +2520,7 @@ void Assembler::movdqa(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
void Assembler::movdqu(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2628,8 +2528,7 @@ void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
emit_sse_operand(src, dst);
}
void Assembler::movdqu(XMMRegister dst, const Operand& src) {
void Assembler::movdqu(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2637,8 +2536,7 @@ void Assembler::movdqu(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::prefetch(const Operand& src, int level) {
void Assembler::prefetch(Operand src, int level) {
DCHECK(is_uint2(level));
EnsureSpace ensure_space(this);
EMIT(0x0F);
......@@ -2648,8 +2546,7 @@ void Assembler::prefetch(const Operand& src, int level) {
emit_sse_operand(code, src);
}
void Assembler::movsd(const Operand& dst, XMMRegister src ) {
void Assembler::movsd(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0xF2); // double
EMIT(0x0F);
......@@ -2657,8 +2554,7 @@ void Assembler::movsd(const Operand& dst, XMMRegister src ) {
emit_sse_operand(src, dst);
}
void Assembler::movsd(XMMRegister dst, const Operand& src) {
void Assembler::movsd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF2); // double
EMIT(0x0F);
......@@ -2666,8 +2562,7 @@ void Assembler::movsd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movss(const Operand& dst, XMMRegister src ) {
void Assembler::movss(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0xF3); // float
EMIT(0x0F);
......@@ -2675,8 +2570,7 @@ void Assembler::movss(const Operand& dst, XMMRegister src ) {
emit_sse_operand(src, dst);
}
void Assembler::movss(XMMRegister dst, const Operand& src) {
void Assembler::movss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3); // float
EMIT(0x0F);
......@@ -2684,8 +2578,7 @@ void Assembler::movss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movd(XMMRegister dst, const Operand& src) {
void Assembler::movd(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2693,8 +2586,7 @@ void Assembler::movd(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::movd(const Operand& dst, XMMRegister src) {
void Assembler::movd(Operand dst, XMMRegister src) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2816,7 +2708,7 @@ void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::pshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle) {
void Assembler::pshuflw(XMMRegister dst, Operand src, uint8_t shuffle) {
EnsureSpace ensure_space(this);
EMIT(0xF2);
EMIT(0x0F);
......@@ -2825,7 +2717,7 @@ void Assembler::pshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle) {
EMIT(shuffle);
}
void Assembler::pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle) {
void Assembler::pshufd(XMMRegister dst, Operand src, uint8_t shuffle) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2834,7 +2726,7 @@ void Assembler::pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle) {
EMIT(shuffle);
}
void Assembler::pextrb(const Operand& dst, XMMRegister src, int8_t offset) {
void Assembler::pextrb(Operand dst, XMMRegister src, int8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2845,7 +2737,7 @@ void Assembler::pextrb(const Operand& dst, XMMRegister src, int8_t offset) {
EMIT(offset);
}
void Assembler::pextrw(const Operand& dst, XMMRegister src, int8_t offset) {
void Assembler::pextrw(Operand dst, XMMRegister src, int8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2856,7 +2748,7 @@ void Assembler::pextrw(const Operand& dst, XMMRegister src, int8_t offset) {
EMIT(offset);
}
void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
void Assembler::pextrd(Operand dst, XMMRegister src, int8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2867,7 +2759,7 @@ void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
EMIT(offset);
}
void Assembler::insertps(XMMRegister dst, const Operand& src, int8_t offset) {
void Assembler::insertps(XMMRegister dst, Operand src, int8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2878,7 +2770,7 @@ void Assembler::insertps(XMMRegister dst, const Operand& src, int8_t offset) {
EMIT(offset);
}
void Assembler::pinsrb(XMMRegister dst, const Operand& src, int8_t offset) {
void Assembler::pinsrb(XMMRegister dst, Operand src, int8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2889,7 +2781,7 @@ void Assembler::pinsrb(XMMRegister dst, const Operand& src, int8_t offset) {
EMIT(offset);
}
void Assembler::pinsrw(XMMRegister dst, const Operand& src, int8_t offset) {
void Assembler::pinsrw(XMMRegister dst, Operand src, int8_t offset) {
DCHECK(is_uint8(offset));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2899,7 +2791,7 @@ void Assembler::pinsrw(XMMRegister dst, const Operand& src, int8_t offset) {
EMIT(offset);
}
void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
void Assembler::pinsrd(XMMRegister dst, Operand src, int8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2910,8 +2802,7 @@ void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
EMIT(offset);
}
void Assembler::addss(XMMRegister dst, const Operand& src) {
void Assembler::addss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2919,8 +2810,7 @@ void Assembler::addss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::subss(XMMRegister dst, const Operand& src) {
void Assembler::subss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2928,8 +2818,7 @@ void Assembler::subss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::mulss(XMMRegister dst, const Operand& src) {
void Assembler::mulss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2937,8 +2826,7 @@ void Assembler::mulss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::divss(XMMRegister dst, const Operand& src) {
void Assembler::divss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2946,8 +2834,7 @@ void Assembler::divss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::sqrtss(XMMRegister dst, const Operand& src) {
void Assembler::sqrtss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2955,16 +2842,14 @@ void Assembler::sqrtss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::ucomiss(XMMRegister dst, const Operand& src) {
void Assembler::ucomiss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x2E);
emit_sse_operand(dst, src);
}
void Assembler::maxss(XMMRegister dst, const Operand& src) {
void Assembler::maxss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2972,8 +2857,7 @@ void Assembler::maxss(XMMRegister dst, const Operand& src) {
emit_sse_operand(dst, src);
}
void Assembler::minss(XMMRegister dst, const Operand& src) {
void Assembler::minss(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
EMIT(0xF3);
EMIT(0x0F);
......@@ -2984,7 +2868,7 @@ void Assembler::minss(XMMRegister dst, const Operand& src) {
// AVX instructions
void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
Operand src2) {
DCHECK(IsEnabled(FMA3));
EnsureSpace ensure_space(this);
emit_vex_prefix(src1, kLIG, k66, k0F38, kW1);
......@@ -2992,9 +2876,8 @@ void Assembler::vfmasd(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
Operand src2) {
DCHECK(IsEnabled(FMA3));
EnsureSpace ensure_space(this);
emit_vex_prefix(src1, kLIG, k66, k0F38, kW0);
......@@ -3002,37 +2885,29 @@ void Assembler::vfmass(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::vsd(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
void Assembler::vsd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(op, dst, src1, src2, kF2, k0F, kWIG);
}
void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(op, dst, src1, src2, kF3, k0F, kWIG);
}
void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(op, dst, src1, src2, kNone, k0F, kWIG);
}
void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2) {
void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
vinstr(op, dst, src1, src2, k66, k0F, kWIG);
}
void Assembler::vcmpps(XMMRegister dst, XMMRegister src1, const Operand& src2,
void Assembler::vcmpps(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t cmp) {
vps(0xC2, dst, src1, src2);
EMIT(cmp);
}
void Assembler::vshufps(XMMRegister dst, XMMRegister src1, const Operand& src2,
void Assembler::vshufps(XMMRegister dst, XMMRegister src1, Operand src2,
byte imm8) {
DCHECK(is_uint8(imm8));
vps(0xC6, dst, src1, src2);
......@@ -3075,56 +2950,56 @@ void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int8_t imm8) {
EMIT(imm8);
}
void Assembler::vpshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle) {
void Assembler::vpshuflw(XMMRegister dst, Operand src, uint8_t shuffle) {
vinstr(0x70, dst, xmm0, src, kF2, k0F, kWIG);
EMIT(shuffle);
}
void Assembler::vpshufd(XMMRegister dst, const Operand& src, uint8_t shuffle) {
void Assembler::vpshufd(XMMRegister dst, Operand src, uint8_t shuffle) {
vinstr(0x70, dst, xmm0, src, k66, k0F, kWIG);
EMIT(shuffle);
}
void Assembler::vpextrb(const Operand& dst, XMMRegister src, int8_t offset) {
void Assembler::vpextrb(Operand dst, XMMRegister src, int8_t offset) {
vinstr(0x14, src, xmm0, dst, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpextrw(const Operand& dst, XMMRegister src, int8_t offset) {
void Assembler::vpextrw(Operand dst, XMMRegister src, int8_t offset) {
vinstr(0x15, src, xmm0, dst, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpextrd(const Operand& dst, XMMRegister src, int8_t offset) {
void Assembler::vpextrd(Operand dst, XMMRegister src, int8_t offset) {
vinstr(0x16, src, xmm0, dst, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vinsertps(XMMRegister dst, XMMRegister src1,
const Operand& src2, int8_t offset) {
void Assembler::vinsertps(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
vinstr(0x21, dst, src1, src2, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpinsrb(XMMRegister dst, XMMRegister src1, const Operand& src2,
void Assembler::vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
vinstr(0x20, dst, src1, src2, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpinsrw(XMMRegister dst, XMMRegister src1, const Operand& src2,
void Assembler::vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
vinstr(0xC4, dst, src1, src2, k66, k0F, kWIG);
EMIT(offset);
}
void Assembler::vpinsrd(XMMRegister dst, XMMRegister src1, const Operand& src2,
void Assembler::vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
vinstr(0x22, dst, src1, src2, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) {
void Assembler::bmi1(byte op, Register reg, Register vreg, Operand rm) {
DCHECK(IsEnabled(BMI1));
EnsureSpace ensure_space(this);
emit_vex_prefix(vreg, kLZ, kNone, k0F38, kW0);
......@@ -3132,8 +3007,7 @@ void Assembler::bmi1(byte op, Register reg, Register vreg, const Operand& rm) {
emit_operand(reg, rm);
}
void Assembler::tzcnt(Register dst, const Operand& src) {
void Assembler::tzcnt(Register dst, Operand src) {
DCHECK(IsEnabled(BMI1));
EnsureSpace ensure_space(this);
EMIT(0xF3);
......@@ -3142,8 +3016,7 @@ void Assembler::tzcnt(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::lzcnt(Register dst, const Operand& src) {
void Assembler::lzcnt(Register dst, Operand src) {
DCHECK(IsEnabled(LZCNT));
EnsureSpace ensure_space(this);
EMIT(0xF3);
......@@ -3152,8 +3025,7 @@ void Assembler::lzcnt(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::popcnt(Register dst, const Operand& src) {
void Assembler::popcnt(Register dst, Operand src) {
DCHECK(IsEnabled(POPCNT));
EnsureSpace ensure_space(this);
EMIT(0xF3);
......@@ -3162,9 +3034,8 @@ void Assembler::popcnt(Register dst, const Operand& src) {
emit_operand(dst, src);
}
void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg,
const Operand& rm) {
Operand rm) {
DCHECK(IsEnabled(BMI2));
EnsureSpace ensure_space(this);
emit_vex_prefix(vreg, kLZ, pp, k0F38, kW0);
......@@ -3172,8 +3043,7 @@ void Assembler::bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg,
emit_operand(reg, rm);
}
void Assembler::rorx(Register dst, const Operand& src, byte imm8) {
void Assembler::rorx(Register dst, Operand src, byte imm8) {
DCHECK(IsEnabled(BMI2));
DCHECK(is_uint8(imm8));
Register vreg = Register::from_code<0>(); // VEX.vvvv unused
......@@ -3184,7 +3054,7 @@ void Assembler::rorx(Register dst, const Operand& src, byte imm8) {
EMIT(imm8);
}
void Assembler::sse2_instr(XMMRegister dst, const Operand& src, byte prefix,
void Assembler::sse2_instr(XMMRegister dst, Operand src, byte prefix,
byte escape, byte opcode) {
EnsureSpace ensure_space(this);
EMIT(prefix);
......@@ -3193,7 +3063,7 @@ void Assembler::sse2_instr(XMMRegister dst, const Operand& src, byte prefix,
emit_sse_operand(dst, src);
}
void Assembler::ssse3_instr(XMMRegister dst, const Operand& src, byte prefix,
void Assembler::ssse3_instr(XMMRegister dst, Operand src, byte prefix,
byte escape1, byte escape2, byte opcode) {
DCHECK(IsEnabled(SSSE3));
EnsureSpace ensure_space(this);
......@@ -3204,7 +3074,7 @@ void Assembler::ssse3_instr(XMMRegister dst, const Operand& src, byte prefix,
emit_sse_operand(dst, src);
}
void Assembler::sse4_instr(XMMRegister dst, const Operand& src, byte prefix,
void Assembler::sse4_instr(XMMRegister dst, Operand src, byte prefix,
byte escape1, byte escape2, byte opcode) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
......@@ -3215,9 +3085,8 @@ void Assembler::sse4_instr(XMMRegister dst, const Operand& src, byte prefix,
emit_sse_operand(dst, src);
}
void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1,
const Operand& src2, SIMDPrefix pp, LeadingOpcode m,
VexW w) {
void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
SIMDPrefix pp, LeadingOpcode m, VexW w) {
DCHECK(IsEnabled(AVX));
EnsureSpace ensure_space(this);
emit_vex_prefix(src1, kL128, pp, m, w);
......@@ -3225,7 +3094,7 @@ void Assembler::vinstr(byte op, XMMRegister dst, XMMRegister src1,
emit_sse_operand(dst, src2);
}
void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
void Assembler::emit_sse_operand(XMMRegister reg, Operand adr) {
Register ireg = Register::from_code(reg.code());
emit_operand(ireg, adr);
}
......@@ -3345,8 +3214,7 @@ void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
}
}
void Assembler::emit_operand(Register reg, const Operand& adr) {
void Assembler::emit_operand(Register reg, Operand adr) {
const unsigned length = adr.len_;
DCHECK_GT(length, 0);
......
src/ia32/assembler-ia32.h
View file @ c1eaae64
......@@ -322,8 +322,7 @@ enum ScaleFactor {
times_twice_pointer_size = times_8
};
class Operand BASE_EMBEDDED {
class Operand {
public:
// reg
INLINE(explicit Operand(Register reg)) { set_modrm(3, reg); }
......@@ -416,13 +415,17 @@ class Operand BASE_EMBEDDED {
byte buf_[6];
// The number of bytes in buf_.
unsigned int len_;
uint8_t len_;
// Only valid if len_ > 4.
RelocInfo::Mode rmode_;
// TODO(clemensh): Get rid of this friendship, or make Operand immutable.
friend class Assembler;
};
static_assert(sizeof(Operand) <= 2 * kPointerSize,
"Operand must be small enough to pass it by value");
static_assert(IS_TRIVIALLY_COPYABLE(Operand),
"Operand must be trivially copyable to pass it by value");
// -----------------------------------------------------------------------------
// A Displacement describes the 32bit immediate field of an instruction which
......@@ -596,54 +599,54 @@ class Assembler : public AssemblerBase {
void push(const Immediate& x);
void push_imm32(int32_t imm32);
void push(Register src);
void push(const Operand& src);
void push(Operand src);
void pop(Register dst);
void pop(const Operand& dst);
void pop(Operand dst);
void enter(const Immediate& size);
void leave();
// Moves
void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
void mov_b(Register dst, const Operand& src);
void mov_b(Register dst, Operand src);
void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
void mov_b(const Operand& dst, int8_t src) { mov_b(dst, Immediate(src)); }
void mov_b(const Operand& dst, const Immediate& src);
void mov_b(const Operand& dst, Register src);
void mov_b(Operand dst, int8_t src) { mov_b(dst, Immediate(src)); }
void mov_b(Operand dst, const Immediate& src);
void mov_b(Operand dst, Register src);
void mov_w(Register dst, const Operand& src);
void mov_w(const Operand& dst, int16_t src) { mov_w(dst, Immediate(src)); }
void mov_w(const Operand& dst, const Immediate& src);
void mov_w(const Operand& dst, Register src);
void mov_w(Register dst, Operand src);
void mov_w(Operand dst, int16_t src) { mov_w(dst, Immediate(src)); }
void mov_w(Operand dst, const Immediate& src);
void mov_w(Operand dst, Register src);
void mov(Register dst, int32_t imm32);
void mov(Register dst, const Immediate& x);
void mov(Register dst, Handle<HeapObject> handle);
void mov(Register dst, const Operand& src);
void mov(Register dst, Operand src);
void mov(Register dst, Register src);
void mov(const Operand& dst, const Immediate& x);
void mov(const Operand& dst, Handle<HeapObject> handle);
void mov(const Operand& dst, Register src);
void mov(const Operand& dst, Address src, RelocInfo::Mode);
void mov(Operand dst, const Immediate& x);
void mov(Operand dst, Handle<HeapObject> handle);
void mov(Operand dst, Register src);
void mov(Operand dst, Address src, RelocInfo::Mode);
void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
void movsx_b(Register dst, const Operand& src);
void movsx_b(Register dst, Operand src);
void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
void movsx_w(Register dst, const Operand& src);
void movsx_w(Register dst, Operand src);
void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
void movzx_b(Register dst, const Operand& src);
void movzx_b(Register dst, Operand src);
void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
void movzx_w(Register dst, const Operand& src);
void movzx_w(Register dst, Operand src);
// Conditional moves
void cmov(Condition cc, Register dst, Register src) {
cmov(cc, dst, Operand(src));
}
void cmov(Condition cc, Register dst, const Operand& src);
void cmov(Condition cc, Register dst, Operand src);
// Flag management.
void cld();
......@@ -655,17 +658,17 @@ class Assembler : public AssemblerBase {
// Exchange
void xchg(Register dst, Register src);
void xchg(Register dst, const Operand& src);
void xchg_b(Register reg, const Operand& op);
void xchg_w(Register reg, const Operand& op);
void xchg(Register dst, Operand src);
void xchg_b(Register reg, Operand op);
void xchg_w(Register reg, Operand op);
// Lock prefix
void lock();
// CompareExchange
void cmpxchg(const Operand& dst, Register src);
void cmpxchg_b(const Operand& dst, Register src);
void cmpxchg_w(const Operand& dst, Register src);
void cmpxchg(Operand dst, Register src);
void cmpxchg_b(Operand dst, Register src);
void cmpxchg_w(Operand dst, Register src);
// Memory Fence
void lfence();
......@@ -674,151 +677,151 @@ class Assembler : public AssemblerBase {
// Arithmetics
void adc(Register dst, int32_t imm32);
void adc(Register dst, const Operand& src);
void adc(Register dst, Operand src);
void add(Register dst, Register src) { add(dst, Operand(src)); }
void add(Register dst, const Operand& src);
void add(const Operand& dst, Register src);
void add(Register dst, Operand src);
void add(Operand dst, Register src);
void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
void add(const Operand& dst, const Immediate& x);
void add(Operand dst, const Immediate& x);
void and_(Register dst, int32_t imm32);
void and_(Register dst, const Immediate& x);
void and_(Register dst, Register src) { and_(dst, Operand(src)); }
void and_(Register dst, const Operand& src);
void and_(const Operand& dst, Register src);
void and_(const Operand& dst, const Immediate& x);
void and_(Register dst, Operand src);
void and_(Operand dst, Register src);
void and_(Operand dst, const Immediate& x);
void cmpb(Register reg, Immediate imm8) { cmpb(Operand(reg), imm8); }
void cmpb(const Operand& op, Immediate imm8);
void cmpb(Register reg, const Operand& op);
void cmpb(const Operand& op, Register reg);
void cmpb(Operand op, Immediate imm8);
void cmpb(Register reg, Operand op);
void cmpb(Operand op, Register reg);
void cmpb(Register dst, Register src) { cmpb(Operand(dst), src); }
void cmpb_al(const Operand& op);
void cmpw_ax(const Operand& op);
void cmpw(const Operand& dst, Immediate src);
void cmpb_al(Operand op);
void cmpw_ax(Operand op);
void cmpw(Operand dst, Immediate src);
void cmpw(Register dst, Immediate src) { cmpw(Operand(dst), src); }
void cmpw(Register dst, const Operand& src);
void cmpw(Register dst, Operand src);
void cmpw(Register dst, Register src) { cmpw(Operand(dst), src); }
void cmpw(const Operand& dst, Register src);
void cmpw(Operand dst, Register src);
void cmp(Register reg, int32_t imm32);
void cmp(Register reg, Handle<HeapObject> handle);
void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
void cmp(Register reg, const Operand& op);
void cmp(Register reg, Operand op);
void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
void cmp(const Operand& op, Register reg);
void cmp(const Operand& op, const Immediate& imm);
void cmp(const Operand& op, Handle<HeapObject> handle);
void cmp(Operand op, Register reg);
void cmp(Operand op, const Immediate& imm);
void cmp(Operand op, Handle<HeapObject> handle);
void dec_b(Register dst);
void dec_b(const Operand& dst);
void dec_b(Operand dst);
void dec(Register dst);
void dec(const Operand& dst);
void dec(Operand dst);
void cdq();
void idiv(Register src) { idiv(Operand(src)); }
void idiv(const Operand& src);
void idiv(Operand src);
void div(Register src) { div(Operand(src)); }
void div(const Operand& src);
void div(Operand src);
// Signed multiply instructions.
void imul(Register src); // edx:eax = eax * src.
void imul(Register dst, Register src) { imul(dst, Operand(src)); }
void imul(Register dst, const Operand& src); // dst = dst * src.
void imul(Register dst, Operand src); // dst = dst * src.
void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
void imul(Register dst, const Operand& src, int32_t imm32);
void imul(Register dst, Operand src, int32_t imm32);
void inc(Register dst);
void inc(const Operand& dst);
void inc(Operand dst);
void lea(Register dst, const Operand& src);
void lea(Register dst, Operand src);
// Unsigned multiply instruction.
void mul(Register src); // edx:eax = eax * reg.
void neg(Register dst);
void neg(const Operand& dst);
void neg(Operand dst);
void not_(Register dst);
void not_(const Operand& dst);
void not_(Operand dst);
void or_(Register dst, int32_t imm32);
void or_(Register dst, Register src) { or_(dst, Operand(src)); }
void or_(Register dst, const Operand& src);
void or_(const Operand& dst, Register src);
void or_(Register dst, Operand src);
void or_(Operand dst, Register src);
void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
void or_(const Operand& dst, const Immediate& x);
void or_(Operand dst, const Immediate& x);
void rcl(Register dst, uint8_t imm8);
void rcr(Register dst, uint8_t imm8);
void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
void ror(const Operand& dst, uint8_t imm8);
void ror(Operand dst, uint8_t imm8);
void ror_cl(Register dst) { ror_cl(Operand(dst)); }
void ror_cl(const Operand& dst);
void ror_cl(Operand dst);
void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
void sar(const Operand& dst, uint8_t imm8);
void sar(Operand dst, uint8_t imm8);
void sar_cl(Register dst) { sar_cl(Operand(dst)); }
void sar_cl(const Operand& dst);
void sar_cl(Operand dst);
void sbb(Register dst, const Operand& src);
void sbb(Register dst, Operand src);
void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
void shl(const Operand& dst, uint8_t imm8);
void shl(Operand dst, uint8_t imm8);
void shl_cl(Register dst) { shl_cl(Operand(dst)); }
void shl_cl(const Operand& dst);
void shl_cl(Operand dst);
void shld(Register dst, Register src, uint8_t shift);
void shld_cl(Register dst, Register src);
void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
void shr(const Operand& dst, uint8_t imm8);
void shr(Operand dst, uint8_t imm8);
void shr_cl(Register dst) { shr_cl(Operand(dst)); }
void shr_cl(const Operand& dst);
void shr_cl(Operand dst);
void shrd(Register dst, Register src, uint8_t shift);
void shrd_cl(Register dst, Register src) { shrd_cl(Operand(dst), src); }
void shrd_cl(const Operand& dst, Register src);
void shrd_cl(Operand dst, Register src);
void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
void sub(const Operand& dst, const Immediate& x);
void sub(Operand dst, const Immediate& x);
void sub(Register dst, Register src) { sub(dst, Operand(src)); }
void sub(Register dst, const Operand& src);
void sub(const Operand& dst, Register src);
void sub(Register dst, Operand src);
void sub(Operand dst, Register src);
void sub_sp_32(uint32_t imm);
void test(Register reg, const Immediate& imm);
void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
void test(Register reg, const Operand& op);
void test(const Operand& op, const Immediate& imm);
void test(const Operand& op, Register reg) { test(reg, op); }
void test_b(Register reg, const Operand& op);
void test(Register reg, Operand op);
void test(Operand op, const Immediate& imm);
void test(Operand op, Register reg) { test(reg, op); }
void test_b(Register reg, Operand op);
void test_b(Register reg, Immediate imm8);
void test_b(const Operand& op, Immediate imm8);
void test_b(const Operand& op, Register reg) { test_b(reg, op); }
void test_b(Operand op, Immediate imm8);
void test_b(Operand op, Register reg) { test_b(reg, op); }
void test_b(Register dst, Register src) { test_b(dst, Operand(src)); }
void test_w(Register reg, const Operand& op);
void test_w(Register reg, Operand op);
void test_w(Register reg, Immediate imm16);
void test_w(const Operand& op, Immediate imm16);
void test_w(const Operand& op, Register reg) { test_w(reg, op); }
void test_w(Operand op, Immediate imm16);
void test_w(Operand op, Register reg) { test_w(reg, op); }
void test_w(Register dst, Register src) { test_w(dst, Operand(src)); }
void xor_(Register dst, int32_t imm32);
void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
void xor_(Register dst, const Operand& src);
void xor_(const Operand& dst, Register src);
void xor_(Register dst, Operand src);
void xor_(Operand dst, Register src);
void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
void xor_(const Operand& dst, const Immediate& x);
void xor_(Operand dst, const Immediate& x);
// Bit operations.
void bt(const Operand& dst, Register src);
void bt(Operand dst, Register src);
void bts(Register dst, Register src) { bts(Operand(dst), src); }
void bts(const Operand& dst, Register src);
void bts(Operand dst, Register src);
void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
void bsr(Register dst, const Operand& src);
void bsr(Register dst, Operand src);
void bsf(Register dst, Register src) { bsf(dst, Operand(src)); }
void bsf(Register dst, const Operand& src);
void bsf(Register dst, Operand src);
// Miscellaneous
void hlt();
......@@ -847,9 +850,9 @@ class Assembler : public AssemblerBase {
// Calls
void call(Label* L);
void call(byte* entry, RelocInfo::Mode rmode);
int CallSize(const Operand& adr);
int CallSize(Operand adr);
void call(Register reg) { call(Operand(reg)); }
void call(const Operand& adr);
void call(Operand adr);
int CallSize(Handle<Code> code, RelocInfo::Mode mode);
void call(Handle<Code> code, RelocInfo::Mode rmode);
void call(CodeStub* stub);
......@@ -860,7 +863,7 @@ class Assembler : public AssemblerBase {
void jmp(Label* L, Label::Distance distance = Label::kFar);
void jmp(byte* entry, RelocInfo::Mode rmode);
void jmp(Register reg) { jmp(Operand(reg)); }
void jmp(const Operand& adr);
void jmp(Operand adr);
void jmp(Handle<Code> code, RelocInfo::Mode rmode);
// Conditional jumps
......@@ -880,25 +883,25 @@ class Assembler : public AssemblerBase {
void fldpi();
void fldln2();
void fld_s(const Operand& adr);
void fld_d(const Operand& adr);
void fld_s(Operand adr);
void fld_d(Operand adr);
void fstp_s(const Operand& adr);
void fst_s(const Operand& adr);
void fstp_d(const Operand& adr);
void fst_d(const Operand& adr);
void fstp_s(Operand adr);
void fst_s(Operand adr);
void fstp_d(Operand adr);
void fst_d(Operand adr);
void fild_s(const Operand& adr);
void fild_d(const Operand& adr);
void fild_s(Operand adr);
void fild_d(Operand adr);
void fist_s(const Operand& adr);
void fist_s(Operand adr);
void fistp_s(const Operand& adr);
void fistp_d(const Operand& adr);
void fistp_s(Operand adr);
void fistp_d(Operand adr);
// The fisttp instructions require SSE3.
void fisttp_s(const Operand& adr);
void fisttp_d(const Operand& adr);
void fisttp_s(Operand adr);
void fisttp_d(Operand adr);
void fabs();
void fchs();
......@@ -919,7 +922,7 @@ class Assembler : public AssemblerBase {
void fdiv(int i);
void fdiv_i(int i);
void fisub_s(const Operand& adr);
void fisub_s(Operand adr);
void faddp(int i = 1);
void fsubp(int i = 1);
......@@ -952,62 +955,62 @@ class Assembler : public AssemblerBase {
// SSE instructions
void addss(XMMRegister dst, XMMRegister src) { addss(dst, Operand(src)); }
void addss(XMMRegister dst, const Operand& src);
void addss(XMMRegister dst, Operand src);
void subss(XMMRegister dst, XMMRegister src) { subss(dst, Operand(src)); }
void subss(XMMRegister dst, const Operand& src);
void subss(XMMRegister dst, Operand src);
void mulss(XMMRegister dst, XMMRegister src) { mulss(dst, Operand(src)); }
void mulss(XMMRegister dst, const Operand& src);
void mulss(XMMRegister dst, Operand src);
void divss(XMMRegister dst, XMMRegister src) { divss(dst, Operand(src)); }
void divss(XMMRegister dst, const Operand& src);
void divss(XMMRegister dst, Operand src);
void sqrtss(XMMRegister dst, XMMRegister src) { sqrtss(dst, Operand(src)); }
void sqrtss(XMMRegister dst, const Operand& src);
void sqrtss(XMMRegister dst, Operand src);
void ucomiss(XMMRegister dst, XMMRegister src) { ucomiss(dst, Operand(src)); }
void ucomiss(XMMRegister dst, const Operand& src);
void ucomiss(XMMRegister dst, Operand src);
void movaps(XMMRegister dst, XMMRegister src);
void movups(XMMRegister dst, XMMRegister src);
void movups(XMMRegister dst, const Operand& src);
void movups(const Operand& dst, XMMRegister src);
void movups(XMMRegister dst, Operand src);
void movups(Operand dst, XMMRegister src);
void shufps(XMMRegister dst, XMMRegister src, byte imm8);
void maxss(XMMRegister dst, XMMRegister src) { maxss(dst, Operand(src)); }
void maxss(XMMRegister dst, const Operand& src);
void maxss(XMMRegister dst, Operand src);
void minss(XMMRegister dst, XMMRegister src) { minss(dst, Operand(src)); }
void minss(XMMRegister dst, const Operand& src);
void minss(XMMRegister dst, Operand src);
void andps(XMMRegister dst, const Operand& src);
void andps(XMMRegister dst, Operand src);
void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
void xorps(XMMRegister dst, const Operand& src);
void xorps(XMMRegister dst, Operand src);
void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
void orps(XMMRegister dst, const Operand& src);
void orps(XMMRegister dst, Operand src);
void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
void addps(XMMRegister dst, const Operand& src);
void addps(XMMRegister dst, Operand src);
void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
void subps(XMMRegister dst, const Operand& src);
void subps(XMMRegister dst, Operand src);
void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
void mulps(XMMRegister dst, const Operand& src);
void mulps(XMMRegister dst, Operand src);
void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
void divps(XMMRegister dst, const Operand& src);
void divps(XMMRegister dst, Operand src);
void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
void rcpps(XMMRegister dst, const Operand& src);
void rcpps(XMMRegister dst, Operand src);
void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
void rsqrtps(XMMRegister dst, const Operand& src);
void rsqrtps(XMMRegister dst, Operand src);
void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
void haddps(XMMRegister dst, const Operand& src);
void haddps(XMMRegister dst, Operand src);
void haddps(XMMRegister dst, XMMRegister src) { haddps(dst, Operand(src)); }
void minps(XMMRegister dst, const Operand& src);
void minps(XMMRegister dst, Operand src);
void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
void maxps(XMMRegister dst, const Operand& src);
void maxps(XMMRegister dst, Operand src);
void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
void cmpps(XMMRegister dst, const Operand& src, int8_t cmp);
void cmpps(XMMRegister dst, Operand src, int8_t cmp);
#define SSE_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src) { \
cmpps(dst, Operand(src), imm8); \
} \
void instr##ps(XMMRegister dst, const Operand& src) { cmpps(dst, src, imm8); }
void instr##ps(XMMRegister dst, Operand src) { cmpps(dst, src, imm8); }
SSE_CMP_P(cmpeq, 0x0);
SSE_CMP_P(cmplt, 0x1);
......@@ -1017,54 +1020,54 @@ class Assembler : public AssemblerBase {
#undef SSE_CMP_P
// SSE2 instructions
void cvttss2si(Register dst, const Operand& src);
void cvttss2si(Register dst, Operand src);
void cvttss2si(Register dst, XMMRegister src) {
cvttss2si(dst, Operand(src));
}
void cvttsd2si(Register dst, const Operand& src);
void cvttsd2si(Register dst, Operand src);
void cvttsd2si(Register dst, XMMRegister src) {
cvttsd2si(dst, Operand(src));
}
void cvtsd2si(Register dst, XMMRegister src);
void cvtsi2ss(XMMRegister dst, Register src) { cvtsi2ss(dst, Operand(src)); }
void cvtsi2ss(XMMRegister dst, const Operand& src);
void cvtsi2ss(XMMRegister dst, Operand src);
void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
void cvtsi2sd(XMMRegister dst, const Operand& src);
void cvtss2sd(XMMRegister dst, const Operand& src);
void cvtsi2sd(XMMRegister dst, Operand src);
void cvtss2sd(XMMRegister dst, Operand src);
void cvtss2sd(XMMRegister dst, XMMRegister src) {
cvtss2sd(dst, Operand(src));
}
void cvtsd2ss(XMMRegister dst, const Operand& src);
void cvtsd2ss(XMMRegister dst, Operand src);
void cvtsd2ss(XMMRegister dst, XMMRegister src) {
cvtsd2ss(dst, Operand(src));
}
void cvtdq2ps(XMMRegister dst, XMMRegister src) {
cvtdq2ps(dst, Operand(src));
}
void cvtdq2ps(XMMRegister dst, const Operand& src);
void cvtdq2ps(XMMRegister dst, Operand src);
void cvttps2dq(XMMRegister dst, XMMRegister src) {
cvttps2dq(dst, Operand(src));
}
void cvttps2dq(XMMRegister dst, const Operand& src);
void cvttps2dq(XMMRegister dst, Operand src);
void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); }
void addsd(XMMRegister dst, const Operand& src);
void addsd(XMMRegister dst, Operand src);
void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); }
void subsd(XMMRegister dst, const Operand& src);
void subsd(XMMRegister dst, Operand src);
void mulsd(XMMRegister dst, XMMRegister src) { mulsd(dst, Operand(src)); }
void mulsd(XMMRegister dst, const Operand& src);
void mulsd(XMMRegister dst, Operand src);
void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); }
void divsd(XMMRegister dst, const Operand& src);
void divsd(XMMRegister dst, Operand src);
void xorpd(XMMRegister dst, XMMRegister src);
void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); }
void sqrtsd(XMMRegister dst, const Operand& src);
void sqrtsd(XMMRegister dst, Operand src);
void andpd(XMMRegister dst, XMMRegister src);
void orpd(XMMRegister dst, XMMRegister src);
void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
void ucomisd(XMMRegister dst, const Operand& src);
void ucomisd(XMMRegister dst, Operand src);
void roundss(XMMRegister dst, XMMRegister src, RoundingMode mode);
void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
......@@ -1075,15 +1078,15 @@ class Assembler : public AssemblerBase {
void cmpltsd(XMMRegister dst, XMMRegister src);
void maxsd(XMMRegister dst, XMMRegister src) { maxsd(dst, Operand(src)); }
void maxsd(XMMRegister dst, const Operand& src);
void maxsd(XMMRegister dst, Operand src);
void minsd(XMMRegister dst, XMMRegister src) { minsd(dst, Operand(src)); }
void minsd(XMMRegister dst, const Operand& src);
void minsd(XMMRegister dst, Operand src);
void movdqa(XMMRegister dst, const Operand& src);
void movdqa(const Operand& dst, XMMRegister src);
void movdqu(XMMRegister dst, const Operand& src);
void movdqu(const Operand& dst, XMMRegister src);
void movdq(bool aligned, XMMRegister dst, const Operand& src) {
void movdqa(XMMRegister dst, Operand src);
void movdqa(Operand dst, XMMRegister src);
void movdqu(XMMRegister dst, Operand src);
void movdqu(Operand dst, XMMRegister src);
void movdq(bool aligned, XMMRegister dst, Operand src) {
if (aligned) {
movdqa(dst, src);
} else {
......@@ -1092,16 +1095,15 @@ class Assembler : public AssemblerBase {
}
void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
void movd(XMMRegister dst, const Operand& src);
void movd(XMMRegister dst, Operand src);
void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
void movd(const Operand& dst, XMMRegister src);
void movd(Operand dst, XMMRegister src);
void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
void movsd(XMMRegister dst, const Operand& src);
void movsd(const Operand& dst, XMMRegister src);
void movsd(XMMRegister dst, Operand src);
void movsd(Operand dst, XMMRegister src);
void movss(XMMRegister dst, const Operand& src);
void movss(const Operand& dst, XMMRegister src);
void movss(XMMRegister dst, Operand src);
void movss(Operand dst, XMMRegister src);
void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
void extractps(Register dst, XMMRegister src, byte imm8);
......@@ -1121,42 +1123,42 @@ class Assembler : public AssemblerBase {
void pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
pshuflw(dst, Operand(src), shuffle);
}
void pshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle);
void pshuflw(XMMRegister dst, Operand src, uint8_t shuffle);
void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
pshufd(dst, Operand(src), shuffle);
}
void pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle);
void pshufd(XMMRegister dst, Operand src, uint8_t shuffle);
void pextrb(Register dst, XMMRegister src, int8_t offset) {
pextrb(Operand(dst), src, offset);
}
void pextrb(const Operand& dst, XMMRegister src, int8_t offset);
void pextrb(Operand dst, XMMRegister src, int8_t offset);
// Use SSE4_1 encoding for pextrw reg, xmm, imm8 for consistency
void pextrw(Register dst, XMMRegister src, int8_t offset) {
pextrw(Operand(dst), src, offset);
}
void pextrw(const Operand& dst, XMMRegister src, int8_t offset);
void pextrw(Operand dst, XMMRegister src, int8_t offset);
void pextrd(Register dst, XMMRegister src, int8_t offset) {
pextrd(Operand(dst), src, offset);
}
void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
void pextrd(Operand dst, XMMRegister src, int8_t offset);
void insertps(XMMRegister dst, XMMRegister src, int8_t offset) {
insertps(dst, Operand(src), offset);
}
void insertps(XMMRegister dst, const Operand& src, int8_t offset);
void insertps(XMMRegister dst, Operand src, int8_t offset);
void pinsrb(XMMRegister dst, Register src, int8_t offset) {
pinsrb(dst, Operand(src), offset);
}
void pinsrb(XMMRegister dst, const Operand& src, int8_t offset);
void pinsrb(XMMRegister dst, Operand src, int8_t offset);
void pinsrw(XMMRegister dst, Register src, int8_t offset) {
pinsrw(dst, Operand(src), offset);
}
void pinsrw(XMMRegister dst, const Operand& src, int8_t offset);
void pinsrw(XMMRegister dst, Operand src, int8_t offset);
void pinsrd(XMMRegister dst, Register src, int8_t offset) {
pinsrd(dst, Operand(src), offset);
}
void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
void pinsrd(XMMRegister dst, Operand src, int8_t offset);
// AVX instructions
void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1168,13 +1170,13 @@ class Assembler : public AssemblerBase {
void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmadd231sd(dst, src1, Operand(src2));
}
void vfmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x99, dst, src1, src2);
}
void vfmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xa9, dst, src1, src2);
}
void vfmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xb9, dst, src1, src2);
}
void vfmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1186,13 +1188,13 @@ class Assembler : public AssemblerBase {
void vfmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmsub231sd(dst, src1, Operand(src2));
}
void vfmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x9b, dst, src1, src2);
}
void vfmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xab, dst, src1, src2);
}
void vfmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xbb, dst, src1, src2);
}
void vfnmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1204,13 +1206,13 @@ class Assembler : public AssemblerBase {
void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfnmadd231sd(dst, src1, Operand(src2));
}
void vfnmadd132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x9d, dst, src1, src2);
}
void vfnmadd213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xad, dst, src1, src2);
}
void vfnmadd231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xbd, dst, src1, src2);
}
void vfnmsub132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1222,16 +1224,16 @@ class Assembler : public AssemblerBase {
void vfnmsub231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfnmsub231sd(dst, src1, Operand(src2));
}
void vfnmsub132sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub132sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0x9f, dst, src1, src2);
}
void vfnmsub213sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub213sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xaf, dst, src1, src2);
}
void vfnmsub231sd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub231sd(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmasd(0xbf, dst, src1, src2);
}
void vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vfmasd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vfmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmadd132ss(dst, src1, Operand(src2));
......@@ -1242,13 +1244,13 @@ class Assembler : public AssemblerBase {
void vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmadd231ss(dst, src1, Operand(src2));
}
void vfmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x99, dst, src1, src2);
}
void vfmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xa9, dst, src1, src2);
}
void vfmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xb9, dst, src1, src2);
}
void vfmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1260,13 +1262,13 @@ class Assembler : public AssemblerBase {
void vfmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfmsub231ss(dst, src1, Operand(src2));
}
void vfmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x9b, dst, src1, src2);
}
void vfmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xab, dst, src1, src2);
}
void vfmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xbb, dst, src1, src2);
}
void vfnmadd132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1278,13 +1280,13 @@ class Assembler : public AssemblerBase {
void vfnmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfnmadd231ss(dst, src1, Operand(src2));
}
void vfnmadd132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x9d, dst, src1, src2);
}
void vfnmadd213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xad, dst, src1, src2);
}
void vfnmadd231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmadd231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xbd, dst, src1, src2);
}
void vfnmsub132ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1296,101 +1298,101 @@ class Assembler : public AssemblerBase {
void vfnmsub231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vfnmsub231ss(dst, src1, Operand(src2));
}
void vfnmsub132ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub132ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0x9f, dst, src1, src2);
}
void vfnmsub213ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub213ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xaf, dst, src1, src2);
}
void vfnmsub231ss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vfnmsub231ss(XMMRegister dst, XMMRegister src1, Operand src2) {
vfmass(0xbf, dst, src1, src2);
}
void vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vfmass(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vaddsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vaddsd(dst, src1, Operand(src2));
}
void vaddsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vaddsd(XMMRegister dst, XMMRegister src1, Operand src2) {
vsd(0x58, dst, src1, src2);
}
void vsubsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsubsd(dst, src1, Operand(src2));
}
void vsubsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vsubsd(XMMRegister dst, XMMRegister src1, Operand src2) {
vsd(0x5c, dst, src1, src2);
}
void vmulsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vmulsd(dst, src1, Operand(src2));
}
void vmulsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vmulsd(XMMRegister dst, XMMRegister src1, Operand src2) {
vsd(0x59, dst, src1, src2);
}
void vdivsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vdivsd(dst, src1, Operand(src2));
}
void vdivsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vdivsd(XMMRegister dst, XMMRegister src1, Operand src2) {
vsd(0x5e, dst, src1, src2);
}
void vmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vmaxsd(dst, src1, Operand(src2));
}
void vmaxsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vmaxsd(XMMRegister dst, XMMRegister src1, Operand src2) {
vsd(0x5f, dst, src1, src2);
}
void vminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vminsd(dst, src1, Operand(src2));
}
void vminsd(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vminsd(XMMRegister dst, XMMRegister src1, Operand src2) {
vsd(0x5d, dst, src1, src2);
}
void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vsd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vaddss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vaddss(dst, src1, Operand(src2));
}
void vaddss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vaddss(XMMRegister dst, XMMRegister src1, Operand src2) {
vss(0x58, dst, src1, src2);
}
void vsubss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vsubss(dst, src1, Operand(src2));
}
void vsubss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vsubss(XMMRegister dst, XMMRegister src1, Operand src2) {
vss(0x5c, dst, src1, src2);
}
void vmulss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vmulss(dst, src1, Operand(src2));
}
void vmulss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vmulss(XMMRegister dst, XMMRegister src1, Operand src2) {
vss(0x59, dst, src1, src2);
}
void vdivss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vdivss(dst, src1, Operand(src2));
}
void vdivss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vdivss(XMMRegister dst, XMMRegister src1, Operand src2) {
vss(0x5e, dst, src1, src2);
}
void vmaxss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vmaxss(dst, src1, Operand(src2));
}
void vmaxss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vmaxss(XMMRegister dst, XMMRegister src1, Operand src2) {
vss(0x5f, dst, src1, src2);
}
void vminss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
vminss(dst, src1, Operand(src2));
}
void vminss(XMMRegister dst, XMMRegister src1, const Operand& src2) {
void vminss(XMMRegister dst, XMMRegister src1, Operand src2) {
vss(0x5d, dst, src1, src2);
}
void vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vrcpps(XMMRegister dst, XMMRegister src) { vrcpps(dst, Operand(src)); }
void vrcpps(XMMRegister dst, const Operand& src) {
void vrcpps(XMMRegister dst, Operand src) {
vinstr(0x53, dst, xmm0, src, kNone, k0F, kWIG);
}
void vrsqrtps(XMMRegister dst, XMMRegister src) {
vrsqrtps(dst, Operand(src));
}
void vrsqrtps(XMMRegister dst, const Operand& src) {
void vrsqrtps(XMMRegister dst, Operand src) {
vinstr(0x52, dst, xmm0, src, kNone, k0F, kWIG);
}
void vmovaps(XMMRegister dst, XMMRegister src) {
......@@ -1399,8 +1401,7 @@ class Assembler : public AssemblerBase {
void vshufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) {
vshufps(dst, src1, Operand(src2), imm8);
}
void vshufps(XMMRegister dst, XMMRegister src1, const Operand& src2,
byte imm8);
void vshufps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8);
void vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpslld(XMMRegister dst, XMMRegister src, int8_t imm8);
......@@ -1412,75 +1413,72 @@ class Assembler : public AssemblerBase {
void vpshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
vpshuflw(dst, Operand(src), shuffle);
}
void vpshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle);
void vpshuflw(XMMRegister dst, Operand src, uint8_t shuffle);
void vpshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
vpshufd(dst, Operand(src), shuffle);
}
void vpshufd(XMMRegister dst, const Operand& src, uint8_t shuffle);
void vpshufd(XMMRegister dst, Operand src, uint8_t shuffle);
void vpextrb(Register dst, XMMRegister src, int8_t offset) {
vpextrb(Operand(dst), src, offset);
}
void vpextrb(const Operand& dst, XMMRegister src, int8_t offset);
void vpextrb(Operand dst, XMMRegister src, int8_t offset);
void vpextrw(Register dst, XMMRegister src, int8_t offset) {
vpextrw(Operand(dst), src, offset);
}
void vpextrw(const Operand& dst, XMMRegister src, int8_t offset);
void vpextrw(Operand dst, XMMRegister src, int8_t offset);
void vpextrd(Register dst, XMMRegister src, int8_t offset) {
vpextrd(Operand(dst), src, offset);
}
void vpextrd(const Operand& dst, XMMRegister src, int8_t offset);
void vpextrd(Operand dst, XMMRegister src, int8_t offset);
void vinsertps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
int8_t offset) {
vinsertps(dst, src1, Operand(src2), offset);
}
void vinsertps(XMMRegister dst, XMMRegister src1, const Operand& src2,
void vinsertps(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset);
void vpinsrb(XMMRegister dst, XMMRegister src1, Register src2,
int8_t offset) {
vpinsrb(dst, src1, Operand(src2), offset);
}
void vpinsrb(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t offset);
void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, int8_t offset);
void vpinsrw(XMMRegister dst, XMMRegister src1, Register src2,
int8_t offset) {
vpinsrw(dst, src1, Operand(src2), offset);
}
void vpinsrw(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t offset);
void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, int8_t offset);
void vpinsrd(XMMRegister dst, XMMRegister src1, Register src2,
int8_t offset) {
vpinsrd(dst, src1, Operand(src2), offset);
}
void vpinsrd(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t offset);
void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t offset);
void vcvtdq2ps(XMMRegister dst, XMMRegister src) {
vcvtdq2ps(dst, Operand(src));
}
void vcvtdq2ps(XMMRegister dst, const Operand& src) {
void vcvtdq2ps(XMMRegister dst, Operand src) {
vinstr(0x5B, dst, xmm0, src, kNone, k0F, kWIG);
}
void vcvttps2dq(XMMRegister dst, XMMRegister src) {
vcvttps2dq(dst, Operand(src));
}
void vcvttps2dq(XMMRegister dst, const Operand& src) {
void vcvttps2dq(XMMRegister dst, Operand src) {
vinstr(0x5B, dst, xmm0, src, kF3, k0F, kWIG);
}
void vmovdqu(XMMRegister dst, const Operand& src) {
void vmovdqu(XMMRegister dst, Operand src) {
vinstr(0x6F, dst, xmm0, src, kF3, k0F, kWIG);
}
void vmovdqu(const Operand& dst, XMMRegister src) {
void vmovdqu(Operand dst, XMMRegister src) {
vinstr(0x7F, src, xmm0, dst, kF3, k0F, kWIG);
}
void vmovd(XMMRegister dst, Register src) { vmovd(dst, Operand(src)); }
void vmovd(XMMRegister dst, const Operand& src) {
void vmovd(XMMRegister dst, Operand src) {
vinstr(0x6E, dst, xmm0, src, k66, k0F, kWIG);
}
void vmovd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
void vmovd(const Operand& dst, XMMRegister src) {
void vmovd(Operand dst, XMMRegister src) {
vinstr(0x7E, src, xmm0, dst, k66, k0F, kWIG);
}
......@@ -1488,76 +1486,76 @@ class Assembler : public AssemblerBase {
void andn(Register dst, Register src1, Register src2) {
andn(dst, src1, Operand(src2));
}
void andn(Register dst, Register src1, const Operand& src2) {
void andn(Register dst, Register src1, Operand src2) {
bmi1(0xf2, dst, src1, src2);
}
void bextr(Register dst, Register src1, Register src2) {
bextr(dst, Operand(src1), src2);
}
void bextr(Register dst, const Operand& src1, Register src2) {
void bextr(Register dst, Operand src1, Register src2) {
bmi1(0xf7, dst, src2, src1);
}
void blsi(Register dst, Register src) { blsi(dst, Operand(src)); }
void blsi(Register dst, const Operand& src) { bmi1(0xf3, ebx, dst, src); }
void blsi(Register dst, Operand src) { bmi1(0xf3, ebx, dst, src); }
void blsmsk(Register dst, Register src) { blsmsk(dst, Operand(src)); }
void blsmsk(Register dst, const Operand& src) { bmi1(0xf3, edx, dst, src); }
void blsmsk(Register dst, Operand src) { bmi1(0xf3, edx, dst, src); }
void blsr(Register dst, Register src) { blsr(dst, Operand(src)); }
void blsr(Register dst, const Operand& src) { bmi1(0xf3, ecx, dst, src); }
void blsr(Register dst, Operand src) { bmi1(0xf3, ecx, dst, src); }
void tzcnt(Register dst, Register src) { tzcnt(dst, Operand(src)); }
void tzcnt(Register dst, const Operand& src);
void tzcnt(Register dst, Operand src);
void lzcnt(Register dst, Register src) { lzcnt(dst, Operand(src)); }
void lzcnt(Register dst, const Operand& src);
void lzcnt(Register dst, Operand src);
void popcnt(Register dst, Register src) { popcnt(dst, Operand(src)); }
void popcnt(Register dst, const Operand& src);
void popcnt(Register dst, Operand src);
void bzhi(Register dst, Register src1, Register src2) {
bzhi(dst, Operand(src1), src2);
}
void bzhi(Register dst, const Operand& src1, Register src2) {
void bzhi(Register dst, Operand src1, Register src2) {
bmi2(kNone, 0xf5, dst, src2, src1);
}
void mulx(Register dst1, Register dst2, Register src) {
mulx(dst1, dst2, Operand(src));
}
void mulx(Register dst1, Register dst2, const Operand& src) {
void mulx(Register dst1, Register dst2, Operand src) {
bmi2(kF2, 0xf6, dst1, dst2, src);
}
void pdep(Register dst, Register src1, Register src2) {
pdep(dst, src1, Operand(src2));
}
void pdep(Register dst, Register src1, const Operand& src2) {
void pdep(Register dst, Register src1, Operand src2) {
bmi2(kF2, 0xf5, dst, src1, src2);
}
void pext(Register dst, Register src1, Register src2) {
pext(dst, src1, Operand(src2));
}
void pext(Register dst, Register src1, const Operand& src2) {
void pext(Register dst, Register src1, Operand src2) {
bmi2(kF3, 0xf5, dst, src1, src2);
}
void sarx(Register dst, Register src1, Register src2) {
sarx(dst, Operand(src1), src2);
}
void sarx(Register dst, const Operand& src1, Register src2) {
void sarx(Register dst, Operand src1, Register src2) {
bmi2(kF3, 0xf7, dst, src2, src1);
}
void shlx(Register dst, Register src1, Register src2) {
shlx(dst, Operand(src1), src2);
}
void shlx(Register dst, const Operand& src1, Register src2) {
void shlx(Register dst, Operand src1, Register src2) {
bmi2(k66, 0xf7, dst, src2, src1);
}
void shrx(Register dst, Register src1, Register src2) {
shrx(dst, Operand(src1), src2);
}
void shrx(Register dst, const Operand& src1, Register src2) {
void shrx(Register dst, Operand src1, Register src2) {
bmi2(kF2, 0xf7, dst, src2, src1);
}
void rorx(Register dst, Register src, byte imm8) {
rorx(dst, Operand(src), imm8);
}
void rorx(Register dst, const Operand& src, byte imm8);
void rorx(Register dst, Operand src, byte imm8);
#define PACKED_OP_LIST(V) \
V(and, 0x54) \
......@@ -1569,34 +1567,33 @@ class Assembler : public AssemblerBase {
V(div, 0x5e) \
V(max, 0x5f)
#define AVX_PACKED_OP_DECLARE(name, opcode) \
void v##name##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vps(opcode, dst, src1, Operand(src2)); \
} \
void v##name##ps(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vps(opcode, dst, src1, src2); \
} \
void v##name##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vpd(opcode, dst, src1, Operand(src2)); \
} \
void v##name##pd(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vpd(opcode, dst, src1, src2); \
#define AVX_PACKED_OP_DECLARE(name, opcode) \
void v##name##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vps(opcode, dst, src1, Operand(src2)); \
} \
void v##name##ps(XMMRegister dst, XMMRegister src1, Operand src2) { \
vps(opcode, dst, src1, src2); \
} \
void v##name##pd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vpd(opcode, dst, src1, Operand(src2)); \
} \
void v##name##pd(XMMRegister dst, XMMRegister src1, Operand src2) { \
vpd(opcode, dst, src1, src2); \
}
PACKED_OP_LIST(AVX_PACKED_OP_DECLARE);
void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vcmpps(XMMRegister dst, XMMRegister src1, const Operand& src2,
int8_t cmp);
#define AVX_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmpps(dst, src1, Operand(src2), imm8); \
} \
void instr##ps(XMMRegister dst, XMMRegister src1, const Operand& src2) { \
vcmpps(dst, src1, src2, imm8); \
void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp);
#define AVX_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmpps(dst, src1, Operand(src2), imm8); \
} \
void instr##ps(XMMRegister dst, XMMRegister src1, Operand src2) { \
vcmpps(dst, src1, src2, imm8); \
}
AVX_CMP_P(vcmpeq, 0x0);
......@@ -1611,7 +1608,7 @@ class Assembler : public AssemblerBase {
void instruction(XMMRegister dst, XMMRegister src) { \
instruction(dst, Operand(src)); \
} \
void instruction(XMMRegister dst, const Operand& src) { \
void instruction(XMMRegister dst, Operand src) { \
sse2_instr(dst, src, 0x##prefix, 0x##escape, 0x##opcode); \
}
......@@ -1622,8 +1619,7 @@ class Assembler : public AssemblerBase {
void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
v##instruction(dst, src1, Operand(src2)); \
} \
void v##instruction(XMMRegister dst, XMMRegister src1, \
const Operand& src2) { \
void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape, kW0); \
}
......@@ -1635,7 +1631,7 @@ class Assembler : public AssemblerBase {
void instruction(XMMRegister dst, XMMRegister src) { \
instruction(dst, Operand(src)); \
} \
void instruction(XMMRegister dst, const Operand& src) { \
void instruction(XMMRegister dst, Operand src) { \
ssse3_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
}
......@@ -1647,7 +1643,7 @@ class Assembler : public AssemblerBase {
void instruction(XMMRegister dst, XMMRegister src) { \
instruction(dst, Operand(src)); \
} \
void instruction(XMMRegister dst, const Operand& src) { \
void instruction(XMMRegister dst, Operand src) { \
sse4_instr(dst, src, 0x##prefix, 0x##escape1, 0x##escape2, 0x##opcode); \
}
......@@ -1659,8 +1655,7 @@ class Assembler : public AssemblerBase {
void v##instruction(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
v##instruction(dst, src1, Operand(src2)); \
} \
void v##instruction(XMMRegister dst, XMMRegister src1, \
const Operand& src2) { \
void v##instruction(XMMRegister dst, XMMRegister src1, Operand src2) { \
vinstr(0x##opcode, dst, src1, src2, k##prefix, k##escape1##escape2, kW0); \
}
......@@ -1671,7 +1666,7 @@ class Assembler : public AssemblerBase {
// Prefetch src position into cache level.
// Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
// non-temporal
void prefetch(const Operand& src, int level);
void prefetch(Operand src, int level);
// TODO(lrn): Need SFENCE for movnt?
// Check the code size generated from label to here.
......@@ -1725,7 +1720,7 @@ class Assembler : public AssemblerBase {
}
protected:
void emit_sse_operand(XMMRegister reg, const Operand& adr);
void emit_sse_operand(XMMRegister reg, Operand adr);
void emit_sse_operand(XMMRegister dst, XMMRegister src);
void emit_sse_operand(Register dst, XMMRegister src);
void emit_sse_operand(XMMRegister dst, Register src);
......@@ -1764,7 +1759,7 @@ class Assembler : public AssemblerBase {
// sel specifies the /n in the modrm byte (see the Intel PRM).
void emit_arith(int sel, Operand dst, const Immediate& x);
void emit_operand(Register reg, const Operand& adr);
void emit_operand(Register reg, Operand adr);
void emit_label(Label* label);
......@@ -1790,18 +1785,17 @@ class Assembler : public AssemblerBase {
inline void emit_disp(Label* L, Displacement::Type type);
inline void emit_near_disp(Label* L);
void sse2_instr(XMMRegister dst, const Operand& src, byte prefix, byte escape,
void sse2_instr(XMMRegister dst, Operand src, byte prefix, byte escape,
byte opcode);
void ssse3_instr(XMMRegister dst, const Operand& src, byte prefix,
byte escape1, byte escape2, byte opcode);
void sse4_instr(XMMRegister dst, const Operand& src, byte prefix,
byte escape1, byte escape2, byte opcode);
void vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2,
void ssse3_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
byte escape2, byte opcode);
void sse4_instr(XMMRegister dst, Operand src, byte prefix, byte escape1,
byte escape2, byte opcode);
void vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2,
SIMDPrefix pp, LeadingOpcode m, VexW w);
// Most BMI instructions are similar.
void bmi1(byte op, Register reg, Register vreg, const Operand& rm);
void bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg,
const Operand& rm);
void bmi1(byte op, Register reg, Register vreg, Operand rm);
void bmi2(SIMDPrefix pp, byte op, Register reg, Register vreg, Operand rm);
// record reloc info for current pc_
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
......
src/ia32/macro-assembler-ia32.cc
View file @ c1eaae64
......@@ -80,9 +80,7 @@ void MacroAssembler::CompareRoot(Register with, Heap::RootListIndex index) {
}
}
void MacroAssembler::CompareRoot(const Operand& with,
Heap::RootListIndex index) {
void MacroAssembler::CompareRoot(Operand with, Heap::RootListIndex index) {
DCHECK(isolate()->heap()->RootCanBeTreatedAsConstant(index));
Handle<Object> object = isolate()->heap()->root_handle(index);
if (object->IsHeapObject()) {
......@@ -194,7 +192,7 @@ void MacroAssembler::DoubleToI(Register result_reg, XMMRegister input_reg,
j(parity_even, is_nan, dst);
}
void TurboAssembler::LoadUint32(XMMRegister dst, const Operand& src) {
void TurboAssembler::LoadUint32(XMMRegister dst, Operand src) {
Label done;
cmp(src, Immediate(0));
ExternalReference uint32_bias = ExternalReference::address_of_uint32_bias();
......@@ -370,7 +368,7 @@ void MacroAssembler::MaybeDropFrames() {
RelocInfo::CODE_TARGET);
}
void TurboAssembler::Cvtsi2sd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Cvtsi2sd(XMMRegister dst, Operand src) {
xorps(dst, dst);
cvtsi2sd(dst, src);
}
......@@ -1167,9 +1165,7 @@ void TurboAssembler::Move(Register dst, const Immediate& x) {
}
}
void TurboAssembler::Move(const Operand& dst, const Immediate& x) {
mov(dst, x);
}
void TurboAssembler::Move(Operand dst, const Immediate& x) { mov(dst, x); }
void TurboAssembler::Move(Register dst, Handle<HeapObject> object) {
mov(dst, object);
......@@ -1238,8 +1234,7 @@ void TurboAssembler::Move(XMMRegister dst, uint64_t src) {
}
}
void TurboAssembler::Pshuflw(XMMRegister dst, const Operand& src,
uint8_t shuffle) {
void TurboAssembler::Pshuflw(XMMRegister dst, Operand src, uint8_t shuffle) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpshuflw(dst, src, shuffle);
......@@ -1248,8 +1243,7 @@ void TurboAssembler::Pshuflw(XMMRegister dst, const Operand& src,
}
}
void TurboAssembler::Pshufd(XMMRegister dst, const Operand& src,
uint8_t shuffle) {
void TurboAssembler::Pshufd(XMMRegister dst, Operand src, uint8_t shuffle) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpshufd(dst, src, shuffle);
......@@ -1258,7 +1252,7 @@ void TurboAssembler::Pshufd(XMMRegister dst, const Operand& src,
}
}
void TurboAssembler::Psignb(XMMRegister dst, const Operand& src) {
void TurboAssembler::Psignb(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignb(dst, dst, src);
......@@ -1272,7 +1266,7 @@ void TurboAssembler::Psignb(XMMRegister dst, const Operand& src) {
UNREACHABLE();
}
void TurboAssembler::Psignw(XMMRegister dst, const Operand& src) {
void TurboAssembler::Psignw(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignw(dst, dst, src);
......@@ -1286,7 +1280,7 @@ void TurboAssembler::Psignw(XMMRegister dst, const Operand& src) {
UNREACHABLE();
}
void TurboAssembler::Psignd(XMMRegister dst, const Operand& src) {
void TurboAssembler::Psignd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignd(dst, dst, src);
......@@ -1300,7 +1294,7 @@ void TurboAssembler::Psignd(XMMRegister dst, const Operand& src) {
UNREACHABLE();
}
void TurboAssembler::Pshufb(XMMRegister dst, const Operand& src) {
void TurboAssembler::Pshufb(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpshufb(dst, dst, src);
......@@ -1362,7 +1356,7 @@ void TurboAssembler::Pextrd(Register dst, XMMRegister src, int8_t imm8) {
movd(dst, xmm0);
}
void TurboAssembler::Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8,
void TurboAssembler::Pinsrd(XMMRegister dst, Operand src, int8_t imm8,
bool is_64_bits) {
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope sse_scope(this, SSE4_1);
......@@ -1390,7 +1384,7 @@ void TurboAssembler::Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8,
}
}
void TurboAssembler::Lzcnt(Register dst, const Operand& src) {
void TurboAssembler::Lzcnt(Register dst, Operand src) {
if (CpuFeatures::IsSupported(LZCNT)) {
CpuFeatureScope scope(this, LZCNT);
lzcnt(dst, src);
......@@ -1404,7 +1398,7 @@ void TurboAssembler::Lzcnt(Register dst, const Operand& src) {
xor_(dst, Immediate(31)); // for x in [0..31], 31^x == 31-x.
}
void TurboAssembler::Tzcnt(Register dst, const Operand& src) {
void TurboAssembler::Tzcnt(Register dst, Operand src) {
if (CpuFeatures::IsSupported(BMI1)) {
CpuFeatureScope scope(this, BMI1);
tzcnt(dst, src);
......@@ -1417,7 +1411,7 @@ void TurboAssembler::Tzcnt(Register dst, const Operand& src) {
bind(&not_zero_src);
}
void TurboAssembler::Popcnt(Register dst, const Operand& src) {
void TurboAssembler::Popcnt(Register dst, Operand src) {
if (CpuFeatures::IsSupported(POPCNT)) {
CpuFeatureScope scope(this, POPCNT);
popcnt(dst, src);
......
src/ia32/macro-assembler-ia32.h
View file @ c1eaae64
......@@ -103,7 +103,7 @@ class TurboAssembler : public Assembler {
// Move if the registers are not identical.
void Move(Register target, Register source);
void Move(const Operand& dst, const Immediate& x);
void Move(Operand dst, const Immediate& x);
// Move an immediate into an XMM register.
void Move(XMMRegister dst, uint32_t src);
......@@ -188,13 +188,13 @@ class TurboAssembler : public Assembler {
void Prologue();
void Lzcnt(Register dst, Register src) { Lzcnt(dst, Operand(src)); }
void Lzcnt(Register dst, const Operand& src);
void Lzcnt(Register dst, Operand src);
void Tzcnt(Register dst, Register src) { Tzcnt(dst, Operand(src)); }
void Tzcnt(Register dst, const Operand& src);
void Tzcnt(Register dst, Operand src);
void Popcnt(Register dst, Register src) { Popcnt(dst, Operand(src)); }
void Popcnt(Register dst, const Operand& src);
void Popcnt(Register dst, Operand src);
void Ret();
......@@ -205,11 +205,11 @@ class TurboAssembler : public Assembler {
void Pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
Pshuflw(dst, Operand(src), shuffle);
}
void Pshuflw(XMMRegister dst, const Operand& src, uint8_t shuffle);
void Pshuflw(XMMRegister dst, Operand src, uint8_t shuffle);
void Pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
Pshufd(dst, Operand(src), shuffle);
}
void Pshufd(XMMRegister dst, const Operand& src, uint8_t shuffle);
void Pshufd(XMMRegister dst, Operand src, uint8_t shuffle);
// SSE/SSE2 instructions with AVX version.
#define AVX_OP2_WITH_TYPE(macro_name, name, dst_type, src_type) \
......@@ -222,12 +222,12 @@ class TurboAssembler : public Assembler {
} \
}
AVX_OP2_WITH_TYPE(Movdqu, movdqu, XMMRegister, const Operand&)
AVX_OP2_WITH_TYPE(Movdqu, movdqu, const Operand&, XMMRegister)
AVX_OP2_WITH_TYPE(Movdqu, movdqu, XMMRegister, Operand)
AVX_OP2_WITH_TYPE(Movdqu, movdqu, Operand, XMMRegister)
AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, Register)
AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, const Operand&)
AVX_OP2_WITH_TYPE(Movd, movd, XMMRegister, Operand)
AVX_OP2_WITH_TYPE(Movd, movd, Register, XMMRegister)
AVX_OP2_WITH_TYPE(Movd, movd, const Operand&, XMMRegister)
AVX_OP2_WITH_TYPE(Movd, movd, Operand, XMMRegister)
#undef AVX_OP2_WITH_TYPE
......@@ -244,7 +244,7 @@ class TurboAssembler : public Assembler {
}
#define AVX_OP3_XO(macro_name, name) \
AVX_OP3_WITH_TYPE(macro_name, name, XMMRegister, XMMRegister) \
AVX_OP3_WITH_TYPE(macro_name, name, XMMRegister, const Operand&)
AVX_OP3_WITH_TYPE(macro_name, name, XMMRegister, Operand)
AVX_OP3_XO(Pcmpeqd, pcmpeqd)
AVX_OP3_XO(Psubb, psubb)
......@@ -257,14 +257,14 @@ class TurboAssembler : public Assembler {
// Non-SSE2 instructions.
void Pshufb(XMMRegister dst, XMMRegister src) { Pshufb(dst, Operand(src)); }
void Pshufb(XMMRegister dst, const Operand& src);
void Pshufb(XMMRegister dst, Operand src);
void Psignb(XMMRegister dst, XMMRegister src) { Psignb(dst, Operand(src)); }
void Psignb(XMMRegister dst, const Operand& src);
void Psignb(XMMRegister dst, Operand src);
void Psignw(XMMRegister dst, XMMRegister src) { Psignw(dst, Operand(src)); }
void Psignw(XMMRegister dst, const Operand& src);
void Psignw(XMMRegister dst, Operand src);
void Psignd(XMMRegister dst, XMMRegister src) { Psignd(dst, Operand(src)); }
void Psignd(XMMRegister dst, const Operand& src);
void Psignd(XMMRegister dst, Operand src);
void Pextrb(Register dst, XMMRegister src, int8_t imm8);
void Pextrw(Register dst, XMMRegister src, int8_t imm8);
......@@ -273,27 +273,27 @@ class TurboAssembler : public Assembler {
bool is_64_bits = false) {
Pinsrd(dst, Operand(src), imm8, is_64_bits);
}
void Pinsrd(XMMRegister dst, const Operand& src, int8_t imm8,
void Pinsrd(XMMRegister dst, Operand src, int8_t imm8,
bool is_64_bits = false);
void LoadUint32(XMMRegister dst, Register src) {
LoadUint32(dst, Operand(src));
}
void LoadUint32(XMMRegister dst, const Operand& src);
void LoadUint32(XMMRegister dst, Operand src);
// Expression support
// cvtsi2sd instruction only writes to the low 64-bit of dst register, which
// hinders register renaming and makes dependence chains longer. So we use
// xorps to clear the dst register before cvtsi2sd to solve this issue.
void Cvtsi2sd(XMMRegister dst, Register src) { Cvtsi2sd(dst, Operand(src)); }
void Cvtsi2sd(XMMRegister dst, const Operand& src);
void Cvtsi2sd(XMMRegister dst, Operand src);
void Cvtui2ss(XMMRegister dst, Register src, Register tmp);
void SlowTruncateToIDelayed(Zone* zone, Register result_reg);
void Push(Register src) { push(src); }
void Push(const Operand& src) { push(src); }
void Push(Operand src) { push(src); }
void Push(Immediate value) { push(value); }
void Push(Handle<HeapObject> handle) { push(Immediate(handle)); }
void Push(Smi* smi) { Push(Immediate(smi)); }
......@@ -355,7 +355,7 @@ class MacroAssembler : public TurboAssembler {
mov(dst, Immediate(x));
}
}
void Set(const Operand& dst, int32_t x) { mov(dst, Immediate(x)); }
void Set(Operand dst, int32_t x) { mov(dst, Immediate(x)); }
// Operations on roots in the root-array.
void LoadRoot(Register destination, Heap::RootListIndex index);
......@@ -363,7 +363,7 @@ class MacroAssembler : public TurboAssembler {
// These methods can only be used with constant roots (i.e. non-writable
// and not in new space).
void CompareRoot(Register with, Heap::RootListIndex index);
void CompareRoot(const Operand& with, Heap::RootListIndex index);
void CompareRoot(Operand with, Heap::RootListIndex index);
void PushRoot(Heap::RootListIndex index);
// Compare the object in a register to a value and jump if they are equal.
......@@ -372,8 +372,7 @@ class MacroAssembler : public TurboAssembler {
CompareRoot(with, index);
j(equal, if_equal, if_equal_distance);
}
void JumpIfRoot(const Operand& with, Heap::RootListIndex index,
Label* if_equal,
void JumpIfRoot(Operand with, Heap::RootListIndex index, Label* if_equal,
Label::Distance if_equal_distance = Label::kFar) {
CompareRoot(with, index);
j(equal, if_equal, if_equal_distance);
......@@ -386,7 +385,7 @@ class MacroAssembler : public TurboAssembler {
CompareRoot(with, index);
j(not_equal, if_not_equal, if_not_equal_distance);
}
void JumpIfNotRoot(const Operand& with, Heap::RootListIndex index,
void JumpIfNotRoot(Operand with, Heap::RootListIndex index,
Label* if_not_equal,
Label::Distance if_not_equal_distance = Label::kFar) {
CompareRoot(with, index);
......@@ -597,7 +596,7 @@ class MacroAssembler : public TurboAssembler {
void Jump(Handle<Code> target, RelocInfo::Mode rmode) { jmp(target, rmode); }
void Pop(Register dst) { pop(dst); }
void Pop(const Operand& dst) { pop(dst); }
void Pop(Operand dst) { pop(dst); }
void PushReturnAddressFrom(Register src) { push(src); }
void PopReturnAddressTo(Register dst) { pop(dst); }
......
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