[wasm simd] Refactor F64x2 Neg and Abs to reuse existing SSE codegen

Bug: v8:8460
Change-Id: I1d05e8a832d1b70f07c6782669c7b07764c7341d
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1708454Reviewed-by: Bill Budge <bbudge@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#62854}

src/compiler/backend/x64/code-generator-x64.cc

@@ -1529,6 +1529,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ bind(ool->exit());
       break;
     }
+    case kX64F64x2Abs:
     case kSSEFloat64Abs: {
       // TODO(bmeurer): Use RIP relative 128-bit constants.
       __ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
@@ -1536,6 +1537,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Andpd(i.OutputDoubleRegister(), kScratchDoubleReg);
       break;
     }
+    case kX64F64x2Neg:
     case kSSEFloat64Neg: {
       // TODO(bmeurer): Use RIP relative 128-bit constants.
       __ Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
@@ -2278,40 +2280,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ movq(i.OutputDoubleRegister(), kScratchRegister);
       break;
     }
-    case kX64F64x2Abs: {
-      // TODO(zhin): look at kSSEFloat64Abs instruction selection and codegen to
-      // avoid having 2 cases here, and potentially share code
-      CpuFeatureScope sse_scope(tasm(), SSE4_1);
-      XMMRegister dst = i.OutputSimd128Register();
-      XMMRegister src = i.InputSimd128Register(0);
-      if (dst == src) {
-        __ pcmpeqq(kScratchDoubleReg, kScratchDoubleReg);
-        __ psrlq(kScratchDoubleReg, 1);
-        __ andpd(dst, kScratchDoubleReg);
-      } else {
-        __ pcmpeqq(dst, dst);
-        __ psrlq(dst, 1);
-        __ andpd(dst, src);
-      }
-      break;
-    }
-    case kX64F64x2Neg: {
-      // TODO(zhin): look at kSSEFloat64Neg instruction selection and codegen to
-      // avoid having 2 cases here, and potentially share code
-      CpuFeatureScope sse_scope(tasm(), SSE4_1);
-      XMMRegister dst = i.OutputSimd128Register();
-      XMMRegister src = i.InputSimd128Register(0);
-      if (dst == src) {
-        __ pcmpeqq(kScratchDoubleReg, kScratchDoubleReg);
-        __ psllq(kScratchDoubleReg, 63);
-        __ xorpd(dst, kScratchDoubleReg);
-      } else {
-        __ pcmpeqq(dst, dst);
-        __ psllq(dst, 63);
-        __ xorpd(dst, src);
-      }
-      break;
-    }
     case kX64F64x2Eq: {
       DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
       __ cmpeqpd(i.OutputSimd128Register(), i.InputSimd128Register(1));

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -2665,8 +2665,6 @@ VISIT_ATOMIC_BINOP(Xor)
   V(I64x2GeU)
 
 #define SIMD_UNOP_LIST(V)   \
-  V(F64x2Abs)               \
-  V(F64x2Neg)               \
   V(F32x4SConvertI32x4)     \
   V(F32x4Abs)               \
   V(F32x4Neg)               \
@@ -2820,6 +2818,18 @@ void InstructionSelector::VisitS128Select(Node* node) {
        g.UseRegister(node->InputAt(2)));
 }
 
+void InstructionSelector::VisitF64x2Abs(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64F64x2Abs, g.DefineSameAsFirst(node),
+       g.UseRegister(node->InputAt(0)));
+}
+
+void InstructionSelector::VisitF64x2Neg(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64F64x2Neg, g.DefineSameAsFirst(node),
+       g.UseRegister(node->InputAt(0)));
+}
+
 void InstructionSelector::VisitF32x4UConvertI32x4(Node* node) {
   X64OperandGenerator g(this);
   Emit(kX64F32x4UConvertI32x4, g.DefineSameAsFirst(node),