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Commit c0b1bcba authored by bbudge's avatar bbudge Committed by Commit bot
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[ARM] Macro-ize SIMD visitors in InstructionSelector. 

- Uses macros for splat, extract lane, replace lane, unary
ops and binary ops.
- Renames ARM SIMD instruction codes to match machine
operator names.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2652893013
Cr-Commit-Position: refs/heads/master@{#42799}
parent 93c65bbf
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Showing with 234 additions and 627 deletions
src/compiler/arm/code-generator-arm.cc
View file @ c0b1bcba
...@@ -1545,12 +1545,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -1545,12 +1545,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmFloat32x4Eq: { case kArmFloat32x4Equal: {
__ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0), __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmFloat32x4Ne: { case kArmFloat32x4NotEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1));
__ vmvn(dst, dst); __ vmvn(dst, dst);
...@@ -1607,35 +1607,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -1607,35 +1607,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt32x4Eq: { case kArmInt32x4Equal: {
__ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt32x4Ne: { case kArmInt32x4NotEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vceq(Neon32, dst, i.InputSimd128Register(0), __ vceq(Neon32, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
__ vmvn(dst, dst); __ vmvn(dst, dst);
break; break;
} }
case kArmInt32x4Gt: { case kArmInt32x4GreaterThan: {
__ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt32x4Ge: { case kArmInt32x4GreaterThanOrEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonS32, dst, i.InputSimd128Register(0), __ vcge(NeonS32, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmUint32x4Gt: { case kArmUint32x4GreaterThan: {
__ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmUint32x4Ge: { case kArmUint32x4GreaterThanOrEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonU32, dst, i.InputSimd128Register(0), __ vcge(NeonU32, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
...@@ -1693,35 +1693,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -1693,35 +1693,35 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt16x8Eq: { case kArmInt16x8Equal: {
__ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt16x8Ne: { case kArmInt16x8NotEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vceq(Neon16, dst, i.InputSimd128Register(0), __ vceq(Neon16, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
__ vmvn(dst, dst); __ vmvn(dst, dst);
break; break;
} }
case kArmInt16x8Gt: { case kArmInt16x8GreaterThan: {
__ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt16x8Ge: { case kArmInt16x8GreaterThanOrEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonS16, dst, i.InputSimd128Register(0), __ vcge(NeonS16, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmUint16x8Gt: { case kArmUint16x8GreaterThan: {
__ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmUint16x8Ge: { case kArmUint16x8GreaterThanOrEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonU16, dst, i.InputSimd128Register(0), __ vcge(NeonU16, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
...@@ -1770,34 +1770,34 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -1770,34 +1770,34 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt8x16Eq: { case kArmInt8x16Equal: {
__ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt8x16Ne: { case kArmInt8x16NotEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1));
__ vmvn(dst, dst); __ vmvn(dst, dst);
break; break;
} }
case kArmInt8x16Gt: { case kArmInt8x16GreaterThan: {
__ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmInt8x16Ge: { case kArmInt8x16GreaterThanOrEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonS8, dst, i.InputSimd128Register(0), __ vcge(NeonS8, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmUint8x16Gt: { case kArmUint8x16GreaterThan: {
__ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
break; break;
} }
case kArmUint8x16Ge: { case kArmUint8x16GreaterThanOrEqual: {
Simd128Register dst = i.OutputSimd128Register(); Simd128Register dst = i.OutputSimd128Register();
__ vcge(NeonU8, dst, i.InputSimd128Register(0), __ vcge(NeonU8, dst, i.InputSimd128Register(0),
i.InputSimd128Register(1)); i.InputSimd128Register(1));
......
src/compiler/arm/instruction-codes-arm.h
View file @ c0b1bcba
...@@ -129,8 +129,8 @@ namespace compiler { ...@@ -129,8 +129,8 @@ namespace compiler {
V(ArmFloat32x4Neg) \ V(ArmFloat32x4Neg) \
V(ArmFloat32x4Add) \ V(ArmFloat32x4Add) \
V(ArmFloat32x4Sub) \ V(ArmFloat32x4Sub) \
V(ArmFloat32x4Eq) \ V(ArmFloat32x4Equal) \
V(ArmFloat32x4Ne) \ V(ArmFloat32x4NotEqual) \
V(ArmInt32x4Splat) \ V(ArmInt32x4Splat) \
V(ArmInt32x4ExtractLane) \ V(ArmInt32x4ExtractLane) \
V(ArmInt32x4ReplaceLane) \ V(ArmInt32x4ReplaceLane) \
...@@ -142,12 +142,12 @@ namespace compiler { ...@@ -142,12 +142,12 @@ namespace compiler {
V(ArmInt32x4Mul) \ V(ArmInt32x4Mul) \
V(ArmInt32x4Min) \ V(ArmInt32x4Min) \
V(ArmInt32x4Max) \ V(ArmInt32x4Max) \
V(ArmInt32x4Eq) \ V(ArmInt32x4Equal) \
V(ArmInt32x4Ne) \ V(ArmInt32x4NotEqual) \
V(ArmInt32x4Gt) \ V(ArmInt32x4GreaterThan) \
V(ArmInt32x4Ge) \ V(ArmInt32x4GreaterThanOrEqual) \
V(ArmUint32x4Gt) \ V(ArmUint32x4GreaterThan) \
V(ArmUint32x4Ge) \ V(ArmUint32x4GreaterThanOrEqual) \
V(ArmSimd32x4Select) \ V(ArmSimd32x4Select) \
V(ArmInt16x8Splat) \ V(ArmInt16x8Splat) \
V(ArmInt16x8ExtractLane) \ V(ArmInt16x8ExtractLane) \
...@@ -158,12 +158,12 @@ namespace compiler { ...@@ -158,12 +158,12 @@ namespace compiler {
V(ArmInt16x8Mul) \ V(ArmInt16x8Mul) \
V(ArmInt16x8Min) \ V(ArmInt16x8Min) \
V(ArmInt16x8Max) \ V(ArmInt16x8Max) \
V(ArmInt16x8Eq) \ V(ArmInt16x8Equal) \
V(ArmInt16x8Ne) \ V(ArmInt16x8NotEqual) \
V(ArmInt16x8Gt) \ V(ArmInt16x8GreaterThan) \
V(ArmInt16x8Ge) \ V(ArmInt16x8GreaterThanOrEqual) \
V(ArmUint16x8Gt) \ V(ArmUint16x8GreaterThan) \
V(ArmUint16x8Ge) \ V(ArmUint16x8GreaterThanOrEqual) \
V(ArmInt8x16Splat) \ V(ArmInt8x16Splat) \
V(ArmInt8x16ExtractLane) \ V(ArmInt8x16ExtractLane) \
V(ArmInt8x16ReplaceLane) \ V(ArmInt8x16ReplaceLane) \
...@@ -173,12 +173,12 @@ namespace compiler { ...@@ -173,12 +173,12 @@ namespace compiler {
V(ArmInt8x16Mul) \ V(ArmInt8x16Mul) \
V(ArmInt8x16Min) \ V(ArmInt8x16Min) \
V(ArmInt8x16Max) \ V(ArmInt8x16Max) \
V(ArmInt8x16Eq) \ V(ArmInt8x16Equal) \
V(ArmInt8x16Ne) \ V(ArmInt8x16NotEqual) \
V(ArmInt8x16Gt) \ V(ArmInt8x16GreaterThan) \
V(ArmInt8x16Ge) \ V(ArmInt8x16GreaterThanOrEqual) \
V(ArmUint8x16Gt) \ V(ArmUint8x16GreaterThan) \
V(ArmUint8x16Ge) V(ArmUint8x16GreaterThanOrEqual)
// Addressing modes represent the "shape" of inputs to an instruction. // Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes // Many instructions support multiple addressing modes. Addressing modes
......
src/compiler/arm/instruction-scheduler-arm.cc
View file @ c0b1bcba
...@@ -117,8 +117,8 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -117,8 +117,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmFloat32x4Neg: case kArmFloat32x4Neg:
case kArmFloat32x4Add: case kArmFloat32x4Add:
case kArmFloat32x4Sub: case kArmFloat32x4Sub:
case kArmFloat32x4Eq: case kArmFloat32x4Equal:
case kArmFloat32x4Ne: case kArmFloat32x4NotEqual:
case kArmInt32x4Splat: case kArmInt32x4Splat:
case kArmInt32x4ExtractLane: case kArmInt32x4ExtractLane:
case kArmInt32x4ReplaceLane: case kArmInt32x4ReplaceLane:
...@@ -130,12 +130,12 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -130,12 +130,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmInt32x4Mul: case kArmInt32x4Mul:
case kArmInt32x4Min: case kArmInt32x4Min:
case kArmInt32x4Max: case kArmInt32x4Max:
case kArmInt32x4Eq: case kArmInt32x4Equal:
case kArmInt32x4Ne: case kArmInt32x4NotEqual:
case kArmInt32x4Gt: case kArmInt32x4GreaterThan:
case kArmInt32x4Ge: case kArmInt32x4GreaterThanOrEqual:
case kArmUint32x4Gt: case kArmUint32x4GreaterThan:
case kArmUint32x4Ge: case kArmUint32x4GreaterThanOrEqual:
case kArmSimd32x4Select: case kArmSimd32x4Select:
case kArmInt16x8Splat: case kArmInt16x8Splat:
case kArmInt16x8ExtractLane: case kArmInt16x8ExtractLane:
...@@ -146,12 +146,12 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -146,12 +146,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmInt16x8Mul: case kArmInt16x8Mul:
case kArmInt16x8Min: case kArmInt16x8Min:
case kArmInt16x8Max: case kArmInt16x8Max:
case kArmInt16x8Eq: case kArmInt16x8Equal:
case kArmInt16x8Ne: case kArmInt16x8NotEqual:
case kArmInt16x8Gt: case kArmInt16x8GreaterThan:
case kArmInt16x8Ge: case kArmInt16x8GreaterThanOrEqual:
case kArmUint16x8Gt: case kArmUint16x8GreaterThan:
case kArmUint16x8Ge: case kArmUint16x8GreaterThanOrEqual:
case kArmInt8x16Splat: case kArmInt8x16Splat:
case kArmInt8x16ExtractLane: case kArmInt8x16ExtractLane:
case kArmInt8x16ReplaceLane: case kArmInt8x16ReplaceLane:
...@@ -161,12 +161,12 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -161,12 +161,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmInt8x16Mul: case kArmInt8x16Mul:
case kArmInt8x16Min: case kArmInt8x16Min:
case kArmInt8x16Max: case kArmInt8x16Max:
case kArmInt8x16Eq: case kArmInt8x16Equal:
case kArmInt8x16Ne: case kArmInt8x16NotEqual:
case kArmInt8x16Gt: case kArmInt8x16GreaterThan:
case kArmInt8x16Ge: case kArmInt8x16GreaterThanOrEqual:
case kArmUint8x16Gt: case kArmUint8x16GreaterThan:
case kArmUint8x16Ge: case kArmUint8x16GreaterThanOrEqual:
return kNoOpcodeFlags; return kNoOpcodeFlags;
case kArmVldrF32: case kArmVldrF32:
......
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