Commit bfcb3f00 authored by Milad Fa's avatar Milad Fa Committed by Commit Bot

PPC [wasm-simd]: Implement saturating rounding multiply high

Bug: v8:10971
Change-Id: Idaa75b5c4d63695dbb8eed2be076f067ff5df9ff
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2623817Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#72050}
parent f9e76d6d
...@@ -1936,7 +1936,9 @@ using Instr = uint32_t; ...@@ -1936,7 +1936,9 @@ using Instr = uint32_t;
/* Vector Select */ \ /* Vector Select */ \
V(vsel, VSEL, 0x1000002A) \ V(vsel, VSEL, 0x1000002A) \
/* Vector Multiply-Sum Signed Halfword Modulo */ \ /* Vector Multiply-Sum Signed Halfword Modulo */ \
V(vmsumshm, VMSUMSHM, 0x10000028) V(vmsumshm, VMSUMSHM, 0x10000028) \
/* Vector Multiply-High-Round-Add Signed Halfword Saturate */ \
V(vmhraddshs, VMHRADDSHS, 0x10000021)
#define PPC_VA_OPCODE_UNUSED_LIST(V) \ #define PPC_VA_OPCODE_UNUSED_LIST(V) \
/* Vector Add Extended & write Carry Unsigned Quadword */ \ /* Vector Add Extended & write Carry Unsigned Quadword */ \
...@@ -1947,8 +1949,6 @@ using Instr = uint32_t; ...@@ -1947,8 +1949,6 @@ using Instr = uint32_t;
V(vmaddfp, VMADDFP, 0x1000002E) \ V(vmaddfp, VMADDFP, 0x1000002E) \
/* Vector Multiply-High-Add Signed Halfword Saturate */ \ /* Vector Multiply-High-Add Signed Halfword Saturate */ \
V(vmhaddshs, VMHADDSHS, 0x10000020) \ V(vmhaddshs, VMHADDSHS, 0x10000020) \
/* Vector Multiply-High-Round-Add Signed Halfword Saturate */ \
V(vmhraddshs, VMHRADDSHS, 0x10000021) \
/* Vector Multiply-Sum Mixed Byte Modulo */ \ /* Vector Multiply-Sum Mixed Byte Modulo */ \
V(vmsummbm, VMSUMMBM, 0x10000025) \ V(vmsummbm, VMSUMMBM, 0x10000025) \
/* Vector Multiply-Sum Signed Halfword Saturate */ \ /* Vector Multiply-Sum Signed Halfword Saturate */ \
......
...@@ -3714,6 +3714,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3714,6 +3714,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break; break;
} }
#undef EXT_ADD_PAIRWISE #undef EXT_ADD_PAIRWISE
case kPPC_I16x8Q15MulRSatS: {
__ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg);
__ vmhraddshs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), kScratchSimd128Reg);
break;
}
case kPPC_StoreCompressTagged: { case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX); ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break; break;
......
...@@ -335,6 +335,7 @@ namespace compiler { ...@@ -335,6 +335,7 @@ namespace compiler {
V(PPC_I16x8BitMask) \ V(PPC_I16x8BitMask) \
V(PPC_I16x8ExtAddPairwiseI8x16S) \ V(PPC_I16x8ExtAddPairwiseI8x16S) \
V(PPC_I16x8ExtAddPairwiseI8x16U) \ V(PPC_I16x8ExtAddPairwiseI8x16U) \
V(PPC_I16x8Q15MulRSatS) \
V(PPC_I8x16Splat) \ V(PPC_I8x16Splat) \
V(PPC_I8x16ExtractLaneU) \ V(PPC_I8x16ExtractLaneU) \
V(PPC_I8x16ExtractLaneS) \ V(PPC_I8x16ExtractLaneS) \
......
...@@ -258,6 +258,7 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -258,6 +258,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I16x8BitMask: case kPPC_I16x8BitMask:
case kPPC_I16x8ExtAddPairwiseI8x16S: case kPPC_I16x8ExtAddPairwiseI8x16S:
case kPPC_I16x8ExtAddPairwiseI8x16U: case kPPC_I16x8ExtAddPairwiseI8x16U:
case kPPC_I16x8Q15MulRSatS:
case kPPC_I8x16Splat: case kPPC_I8x16Splat:
case kPPC_I8x16ExtractLaneU: case kPPC_I8x16ExtractLaneU:
case kPPC_I8x16ExtractLaneS: case kPPC_I8x16ExtractLaneS:
......
...@@ -2210,6 +2210,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2210,6 +2210,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8AddSatU) \ V(I16x8AddSatU) \
V(I16x8SubSatU) \ V(I16x8SubSatU) \
V(I16x8RoundingAverageU) \ V(I16x8RoundingAverageU) \
V(I16x8Q15MulRSatS) \
V(I8x16Add) \ V(I8x16Add) \
V(I8x16Sub) \ V(I8x16Sub) \
V(I8x16Mul) \ V(I8x16Mul) \
......
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