PPC [simd]: cleanup the instruction selector

This CL includes the following changes:
- Avoid using `UniqueRegister` as much as possible
- Try to group opcodes under Binary or Unary when possible

Some codegen ops had to also be modified to avoid using `Temp`
registers.

Change-Id: Ib21ab7a47f600068c8453d48c3549e481a19c328
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3780496Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#82011}

src/compiler/backend/ppc/instruction-selector-ppc.cc

@@ -2239,6 +2239,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Div)              \
   V(F64x2Min)              \
   V(F64x2Max)              \
+  V(F64x2Pmin)             \
+  V(F64x2Pmax)             \
   V(F32x4Add)              \
   V(F32x4Sub)              \
   V(F32x4Mul)              \
@@ -2249,6 +2251,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4Div)              \
   V(F32x4Min)              \
   V(F32x4Max)              \
+  V(F32x4Pmin)             \
+  V(F32x4Pmax)             \
   V(I64x2Add)              \
   V(I64x2Sub)              \
   V(I64x2Mul)              \
@@ -2260,6 +2264,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I64x2ExtMulHighI32x4U) \
   V(I64x2GtS)              \
   V(I64x2GeS)              \
+  V(I64x2Shl)              \
+  V(I64x2ShrS)             \
+  V(I64x2ShrU)             \
   V(I32x4Add)              \
   V(I32x4Sub)              \
   V(I32x4Mul)              \
@@ -2278,6 +2285,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I32x4ExtMulHighI16x8S) \
   V(I32x4ExtMulLowI16x8U)  \
   V(I32x4ExtMulHighI16x8U) \
+  V(I32x4Shl)              \
+  V(I32x4ShrS)             \
+  V(I32x4ShrU)             \
   V(I16x8Add)              \
   V(I16x8Sub)              \
   V(I16x8Mul)              \
@@ -2303,6 +2313,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I16x8ExtMulHighI8x16S) \
   V(I16x8ExtMulLowI8x16U)  \
   V(I16x8ExtMulHighI8x16U) \
+  V(I16x8Shl)              \
+  V(I16x8ShrS)             \
+  V(I16x8ShrU)             \
   V(I8x16Add)              \
   V(I8x16Sub)              \
   V(I8x16MinS)             \
@@ -2323,6 +2336,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16SubSatU)          \
   V(I8x16RoundingAverageU) \
   V(I8x16Swizzle)          \
+  V(I8x16Shl)              \
+  V(I8x16ShrS)             \
+  V(I8x16ShrU)             \
   V(S128And)               \
   V(S128Or)                \
   V(S128Xor)               \
@@ -2338,6 +2354,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2ConvertLowI32x4S)     \
   V(F64x2ConvertLowI32x4U)     \
   V(F64x2PromoteLowF32x4)      \
+  V(F64x2Splat)                \
   V(F32x4Abs)                  \
   V(F32x4Neg)                  \
   V(F32x4Sqrt)                 \
@@ -2347,13 +2364,17 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4Floor)                \
   V(F32x4Trunc)                \
   V(F32x4DemoteF64x2Zero)      \
+  V(F32x4Splat)                \
   V(I64x2Abs)                  \
   V(I64x2Neg)                  \
   V(I64x2SConvertI32x4Low)     \
   V(I64x2SConvertI32x4High)    \
   V(I64x2UConvertI32x4Low)     \
   V(I64x2UConvertI32x4High)    \
+  V(I64x2AllTrue)              \
+  V(I64x2BitMask)              \
   V(I32x4Neg)                  \
+  V(I64x2Splat)                \
   V(I32x4Abs)                  \
   V(I32x4SConvertF32x4)        \
   V(I32x4UConvertF32x4)        \
@@ -2365,48 +2386,28 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I32x4ExtAddPairwiseI16x8U) \
   V(I32x4TruncSatF64x2SZero)   \
   V(I32x4TruncSatF64x2UZero)   \
+  V(I32x4AllTrue)              \
+  V(I32x4BitMask)              \
+  V(I32x4Splat)                \
   V(I16x8Neg)                  \
   V(I16x8Abs)                  \
+  V(I16x8AllTrue)              \
+  V(I16x8BitMask)              \
+  V(I16x8Splat)                \
   V(I8x16Neg)                  \
   V(I8x16Abs)                  \
   V(I8x16Popcnt)               \
+  V(I8x16AllTrue)              \
+  V(I8x16BitMask)              \
+  V(I8x16Splat)                \
   V(I16x8SConvertI8x16Low)     \
   V(I16x8SConvertI8x16High)    \
   V(I16x8UConvertI8x16Low)     \
   V(I16x8UConvertI8x16High)    \
   V(I16x8ExtAddPairwiseI8x16S) \
   V(I16x8ExtAddPairwiseI8x16U) \
-  V(S128Not)
-
-#define SIMD_SHIFT_LIST(V) \
-  V(I64x2Shl)              \
-  V(I64x2ShrS)             \
-  V(I64x2ShrU)             \
-  V(I32x4Shl)              \
-  V(I32x4ShrS)             \
-  V(I32x4ShrU)             \
-  V(I16x8Shl)              \
-  V(I16x8ShrS)             \
-  V(I16x8ShrU)             \
-  V(I8x16Shl)              \
-  V(I8x16ShrS)             \
-  V(I8x16ShrU)
-
-#define SIMD_BOOL_LIST(V) \
-  V(V128AnyTrue)          \
-  V(I64x2AllTrue)         \
-  V(I32x4AllTrue)         \
-  V(I16x8AllTrue)         \
-  V(I8x16AllTrue)
-
-#define SIMD_VISIT_SPLAT(Type)                               \
-  void InstructionSelector::Visit##Type##Splat(Node* node) { \
-    PPCOperandGenerator g(this);                             \
-    Emit(kPPC_##Type##Splat, g.DefineAsRegister(node),       \
-         g.UseRegister(node->InputAt(0)));                   \
-  }
-SIMD_TYPES(SIMD_VISIT_SPLAT)
-#undef SIMD_VISIT_SPLAT
+  V(S128Not)                   \
+  V(V128AnyTrue)
 
 #define SIMD_VISIT_EXTRACT_LANE(Type, Sign)                              \
   void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
@@ -2439,11 +2440,10 @@ SIMD_TYPES(SIMD_VISIT_REPLACE_LANE)
 #define SIMD_VISIT_BINOP(Opcode)                                           \
   void InstructionSelector::Visit##Opcode(Node* node) {                    \
     PPCOperandGenerator g(this);                                           \
-    InstructionOperand temps[] = {g.TempSimd128Register(),                    \
-                                  g.TempSimd128Register(), g.TempRegister()}; \
+    InstructionOperand temps[] = {g.TempRegister()};                       \
     Emit(kPPC_##Opcode, g.DefineAsRegister(node),                          \
-         g.UseUniqueRegister(node->InputAt(0)),                               \
-         g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps);     \
+         g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
+         arraysize(temps), temps);                                         \
   }
 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
 #undef SIMD_VISIT_BINOP
@@ -2452,41 +2452,18 @@ SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
 #define SIMD_VISIT_UNOP(Opcode)                         \
   void InstructionSelector::Visit##Opcode(Node* node) { \
     PPCOperandGenerator g(this);                        \
-    InstructionOperand temps[] = {g.TempSimd128Register()};         \
     Emit(kPPC_##Opcode, g.DefineAsRegister(node),       \
-         g.UseRegister(node->InputAt(0)), arraysize(temps), temps); \
+         g.UseRegister(node->InputAt(0)));              \
   }
 SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
 #undef SIMD_VISIT_UNOP
 #undef SIMD_UNOP_LIST
 
-#define SIMD_VISIT_SHIFT(Opcode)                        \
-  void InstructionSelector::Visit##Opcode(Node* node) { \
-    PPCOperandGenerator g(this);                        \
-    Emit(kPPC_##Opcode, g.DefineAsRegister(node),       \
-         g.UseUniqueRegister(node->InputAt(0)),         \
-         g.UseUniqueRegister(node->InputAt(1)));        \
-  }
-SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT)
-#undef SIMD_VISIT_SHIFT
-#undef SIMD_SHIFT_LIST
-
-#define SIMD_VISIT_BOOL(Opcode)                         \
-  void InstructionSelector::Visit##Opcode(Node* node) { \
-    PPCOperandGenerator g(this);                        \
-    Emit(kPPC_##Opcode, g.DefineAsRegister(node),       \
-         g.UseUniqueRegister(node->InputAt(0)));        \
-  }
-SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
-#undef SIMD_VISIT_BOOL
-#undef SIMD_BOOL_LIST
-
 #define SIMD_VISIT_QFMOP(Opcode)                                           \
   void InstructionSelector::Visit##Opcode(Node* node) {                    \
     PPCOperandGenerator g(this);                                           \
     Emit(kPPC_##Opcode, g.DefineSameAsFirst(node),                         \
-         g.UseUniqueRegister(node->InputAt(0)),         \
-         g.UseUniqueRegister(node->InputAt(1)),         \
+         g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
          g.UseRegister(node->InputAt(2)));                                 \
   }
 SIMD_VISIT_QFMOP(F64x2Qfma)
@@ -2495,32 +2472,6 @@ SIMD_VISIT_QFMOP(F32x4Qfma)
 SIMD_VISIT_QFMOP(F32x4Qfms)
 #undef SIMD_VISIT_QFMOP
 
-#define SIMD_VISIT_BITMASK(Opcode)                                        \
-  void InstructionSelector::Visit##Opcode(Node* node) {                   \
-    PPCOperandGenerator g(this);                                          \
-    InstructionOperand temps[] = {g.TempRegister()};                      \
-    Emit(kPPC_##Opcode, g.DefineAsRegister(node),                         \
-         g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps); \
-  }
-SIMD_VISIT_BITMASK(I8x16BitMask)
-SIMD_VISIT_BITMASK(I16x8BitMask)
-SIMD_VISIT_BITMASK(I32x4BitMask)
-SIMD_VISIT_BITMASK(I64x2BitMask)
-#undef SIMD_VISIT_BITMASK
-
-#define SIMD_VISIT_PMIN_MAX(Type)                                           \
-  void InstructionSelector::Visit##Type(Node* node) {                       \
-    PPCOperandGenerator g(this);                                            \
-    Emit(kPPC_##Type, g.DefineAsRegister(node),                             \
-         g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); \
-  }
-SIMD_VISIT_PMIN_MAX(F64x2Pmin)
-SIMD_VISIT_PMIN_MAX(F32x4Pmin)
-SIMD_VISIT_PMIN_MAX(F64x2Pmax)
-SIMD_VISIT_PMIN_MAX(F32x4Pmax)
-#undef SIMD_VISIT_PMIN_MAX
-#undef SIMD_TYPES
-
 #if V8_ENABLE_WEBASSEMBLY
 void InstructionSelector::VisitI8x16Shuffle(Node* node) {
   uint8_t shuffle[kSimd128Size];
@@ -2539,8 +2490,8 @@ void InstructionSelector::VisitI8x16Shuffle(Node* node) {
                                ? max_index - current_index
                                : total_lane_count - current_index + max_index);
   }
-  Emit(kPPC_I8x16Shuffle, g.DefineAsRegister(node), g.UseUniqueRegister(input0),
-       g.UseUniqueRegister(input1),
+  Emit(kPPC_I8x16Shuffle, g.DefineAsRegister(node), g.UseRegister(input0),
+       g.UseRegister(input1),
        g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped)),
        g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 4)),
        g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 8)),