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Commit bf53970e authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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PPC [simd]: cleanup the instruction selector 

This CL includes the following changes:
- Avoid using `UniqueRegister` as much as possible
- Try to group opcodes under Binary or Unary when possible

Some codegen ops had to also be modified to avoid using `Temp`
registers.

Change-Id: Ib21ab7a47f600068c8453d48c3549e481a19c328
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3780496Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#82011}
parent 8626a1bd
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Showing with 114 additions and 171 deletions
src/compiler/backend/ppc/code-generator-ppc.cc
View file @ bf53970e
......@@ -2377,8 +2377,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
constexpr int lane_width_in_bytes = 8;
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register tempFPReg0 = i.ToSimd128Register(instr->TempAt(0));
Register tempReg1 = i.ToRegister(instr->TempAt(2));
Register tempReg1 = i.ToRegister(instr->TempAt(0));
Register scratch_0 = ip;
Register scratch_1 = r0;
Simd128Register dst = i.OutputSimd128Register();
......@@ -2389,9 +2388,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
if (i > 0) {
__ vextractd(kScratchSimd128Reg, src0,
Operand(1 * lane_width_in_bytes));
__ vextractd(tempFPReg0, src1, Operand(1 * lane_width_in_bytes));
__ vextractd(kScratchSimd128Reg2, src1,
Operand(1 * lane_width_in_bytes));
src0 = kScratchSimd128Reg;
src1 = tempFPReg0;
src1 = kScratchSimd128Reg2;
}
__ mfvsrd(scratch_0, src0);
__ mfvsrd(scratch_1, src1);
......@@ -2432,8 +2432,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg);
__ vmladduhm(dst, src0, src1, kScratchSimd128Reg);
__ vxor(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ vmladduhm(dst, src0, src1, kSimd128RegZero);
break;
}
case kPPC_I8x16Add: {
......@@ -2828,57 +2828,57 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kPPC_I64x2Abs: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 63;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsrad(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(tempFPReg1, src, kScratchSimd128Reg);
__ vsubudm(i.OutputSimd128Register(), tempFPReg1, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsubudm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_I32x4Abs: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 31;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsraw(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(tempFPReg1, src, kScratchSimd128Reg);
__ vsubuwm(i.OutputSimd128Register(), tempFPReg1, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsubuwm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_I16x8Neg: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
Simd128Register dst = i.OutputSimd128Register();
__ vspltish(kScratchSimd128Reg, Operand(1));
__ vnor(tempFPReg1, i.InputSimd128Register(0), i.InputSimd128Register(0));
__ vadduhm(i.OutputSimd128Register(), kScratchSimd128Reg, tempFPReg1);
__ vnor(dst, i.InputSimd128Register(0), i.InputSimd128Register(0));
__ vadduhm(dst, kScratchSimd128Reg, dst);
break;
}
case kPPC_I16x8Abs: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 15;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsrah(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(tempFPReg1, src, kScratchSimd128Reg);
__ vsubuhm(i.OutputSimd128Register(), tempFPReg1, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsubuhm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_I8x16Neg: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
Simd128Register dst = i.OutputSimd128Register();
__ xxspltib(kScratchSimd128Reg, Operand(1));
__ vnor(tempFPReg1, i.InputSimd128Register(0), i.InputSimd128Register(0));
__ vaddubm(i.OutputSimd128Register(), kScratchSimd128Reg, tempFPReg1);
__ vnor(dst, i.InputSimd128Register(0), i.InputSimd128Register(0));
__ vaddubm(dst, kScratchSimd128Reg, dst);
break;
}
case kPPC_I8x16Abs: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
constexpr int shift_bits = 7;
__ xxspltib(kScratchSimd128Reg, Operand(shift_bits));
__ vsrab(kScratchSimd128Reg, src, kScratchSimd128Reg);
__ vxor(tempFPReg1, src, kScratchSimd128Reg);
__ vsububm(i.OutputSimd128Register(), tempFPReg1, kScratchSimd128Reg);
__ vxor(dst, src, kScratchSimd128Reg);
__ vsububm(dst, dst, kScratchSimd128Reg);
break;
}
case kPPC_V128AnyTrue: {
......@@ -2903,9 +2903,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ li(r0, Operand(0)); \
__ li(ip, Operand(1)); \
/* Check if all lanes > 0, if not then return false.*/ \
__ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg); \
__ vxor(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero); \
__ mtcrf(r0, fxm); /* Clear cr6.*/ \
__ opcode(kScratchSimd128Reg, src, kScratchSimd128Reg, SetRC); \
__ opcode(kSimd128RegZero, src, kSimd128RegZero, SetRC); \
__ isel(dst, ip, r0, bit_number);
case kPPC_I64x2AllTrue: {
SIMD_ALL_TRUE(vcmpgtud)
......@@ -3064,8 +3064,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
uint64_t high = make_uint64(i.InputUint32(5), i.InputUint32(4));
__ mov(r0, Operand(low));
__ mov(ip, Operand(high));
__ mtvsrdd(dst, ip, r0);
__ vperm(dst, src0, src1, dst);
__ mtvsrdd(kScratchSimd128Reg, ip, r0);
__ vperm(dst, src0, src1, kScratchSimd128Reg);
break;
}
case kPPC_I16x8AddSatS: {
......@@ -3111,16 +3111,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kPPC_I8x16Swizzle: {
Simd128Register dst = i.OutputSimd128Register(),
src0 = i.InputSimd128Register(0),
src1 = i.InputSimd128Register(1),
tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
src1 = i.InputSimd128Register(1);
// Saturate the indices to 5 bits. Input indices more than 31 should
// return 0.
__ xxspltib(tempFPReg1, Operand(31));
__ vminub(tempFPReg1, src1, tempFPReg1);
__ xxspltib(kScratchSimd128Reg, Operand(31));
__ vminub(kScratchSimd128Reg, src1, kScratchSimd128Reg);
// input needs to be reversed.
__ xxbrq(dst, src0);
__ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg);
__ vperm(dst, dst, kScratchSimd128Reg, tempFPReg1);
__ vxor(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ vperm(dst, dst, kSimd128RegZero, kScratchSimd128Reg);
break;
}
case kPPC_F64x2Qfma: {
......@@ -3185,14 +3184,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
#define F64X2_MIN_MAX_NAN(result) \
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); \
__ xvcmpeqdp(tempFPReg1, i.InputSimd128Register(0), \
__ xvcmpeqdp(kScratchSimd128Reg2, i.InputSimd128Register(0), \
i.InputSimd128Register(0)); \
__ vsel(result, i.InputSimd128Register(0), result, tempFPReg1); \
__ xvcmpeqdp(tempFPReg1, i.InputSimd128Register(1), \
__ vsel(result, i.InputSimd128Register(0), result, kScratchSimd128Reg2); \
__ xvcmpeqdp(kScratchSimd128Reg2, i.InputSimd128Register(1), \
i.InputSimd128Register(1)); \
__ vsel(i.OutputSimd128Register(), i.InputSimd128Register(1), result, \
tempFPReg1); \
kScratchSimd128Reg2); \
/* Use xvmindp to turn any selected SNANs to QNANs. */ \
__ xvmindp(i.OutputSimd128Register(), i.OutputSimd128Register(), \
i.OutputSimd128Register());
......@@ -3295,10 +3293,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
if (CpuFeatures::IsSupported(PPC_10_PLUS)) {
__ vextractbm(i.OutputRegister(), i.InputSimd128Register(0));
} else {
Register temp = i.ToRegister(instr->TempAt(0));
__ mov(temp, Operand(0x8101820283038));
__ mov(kScratchReg, Operand(0x8101820283038));
__ mov(ip, Operand(0x4048505860687078));
__ mtvsrdd(kScratchSimd128Reg, temp, ip);
__ mtvsrdd(kScratchSimd128Reg, kScratchReg, ip);
__ vbpermq(kScratchSimd128Reg, i.InputSimd128Register(0),
kScratchSimd128Reg);
__ vextractuh(kScratchSimd128Reg, kScratchSimd128Reg, Operand(6));
......@@ -3562,13 +3559,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
#undef MAYBE_REVERSE_BYTES
#define EXT_ADD_PAIRWISE(mul_even, mul_odd, add) \
__ mul_even(tempFPReg1, src, kScratchSimd128Reg); \
__ mul_even(kScratchSimd128Reg2, src, kScratchSimd128Reg); \
__ mul_odd(kScratchSimd128Reg, src, kScratchSimd128Reg); \
__ add(dst, tempFPReg1, kScratchSimd128Reg);
__ add(dst, kScratchSimd128Reg2, kScratchSimd128Reg);
case kPPC_I32x4ExtAddPairwiseI16x8S: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vspltish(kScratchSimd128Reg, Operand(1));
EXT_ADD_PAIRWISE(vmulesh, vmulosh, vadduwm)
break;
......@@ -3576,16 +3572,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kPPC_I32x4ExtAddPairwiseI16x8U: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vspltish(kScratchSimd128Reg, Operand(1));
EXT_ADD_PAIRWISE(vmuleuh, vmulouh, vadduwm)
break;
}
case kPPC_I16x8ExtAddPairwiseI8x16S: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ xxspltib(kScratchSimd128Reg, Operand(1));
EXT_ADD_PAIRWISE(vmulesb, vmulosb, vadduhm)
break;
......@@ -3593,7 +3586,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kPPC_I16x8ExtAddPairwiseI8x16U: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ xxspltib(kScratchSimd128Reg, Operand(1));
EXT_ADD_PAIRWISE(vmuleub, vmuloub, vadduhm)
break;
......@@ -3609,14 +3601,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Simd128Register dst = i.OutputSimd128Register(), \
src0 = i.InputSimd128Register(0), \
src1 = i.InputSimd128Register(1); \
__ mul_even(dst, src0, src1); \
__ mul_odd(kScratchSimd128Reg, src0, src1);
__ mul_even(kScratchSimd128Reg, src0, src1); \
__ mul_odd(dst, src0, src1);
case kPPC_I64x2ExtMulLowI32x4S: {
constexpr int lane_width_in_bytes = 8;
EXT_MUL(vmulesw, vmulosw)
__ vextractd(dst, dst, Operand(1 * lane_width_in_bytes));
__ vextractd(kScratchSimd128Reg, kScratchSimd128Reg,
Operand(1 * lane_width_in_bytes));
__ vextractd(dst, dst, Operand(1 * lane_width_in_bytes));
__ vinsertd(dst, kScratchSimd128Reg, Operand(1 * lane_width_in_bytes));
break;
}
......@@ -3629,9 +3621,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kPPC_I64x2ExtMulLowI32x4U: {
constexpr int lane_width_in_bytes = 8;
EXT_MUL(vmuleuw, vmulouw)
__ vextractd(dst, dst, Operand(1 * lane_width_in_bytes));
__ vextractd(kScratchSimd128Reg, kScratchSimd128Reg,
Operand(1 * lane_width_in_bytes));
__ vextractd(dst, dst, Operand(1 * lane_width_in_bytes));
__ vinsertd(dst, kScratchSimd128Reg, Operand(1 * lane_width_in_bytes));
break;
}
......
src/compiler/backend/ppc/instruction-selector-ppc.cc
View file @ bf53970e
......@@ -2239,6 +2239,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Div) \
V(F64x2Min) \
V(F64x2Max) \
V(F64x2Pmin) \
V(F64x2Pmax) \
V(F32x4Add) \
V(F32x4Sub) \
V(F32x4Mul) \
......@@ -2249,6 +2251,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Div) \
V(F32x4Min) \
V(F32x4Max) \
V(F32x4Pmin) \
V(F32x4Pmax) \
V(I64x2Add) \
V(I64x2Sub) \
V(I64x2Mul) \
......@@ -2260,6 +2264,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I64x2ExtMulHighI32x4U) \
V(I64x2GtS) \
V(I64x2GeS) \
V(I64x2Shl) \
V(I64x2ShrS) \
V(I64x2ShrU) \
V(I32x4Add) \
V(I32x4Sub) \
V(I32x4Mul) \
......@@ -2278,6 +2285,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4ExtMulHighI16x8S) \
V(I32x4ExtMulLowI16x8U) \
V(I32x4ExtMulHighI16x8U) \
V(I32x4Shl) \
V(I32x4ShrS) \
V(I32x4ShrU) \
V(I16x8Add) \
V(I16x8Sub) \
V(I16x8Mul) \
......@@ -2303,6 +2313,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8ExtMulHighI8x16S) \
V(I16x8ExtMulLowI8x16U) \
V(I16x8ExtMulHighI8x16U) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8ShrU) \
V(I8x16Add) \
V(I8x16Sub) \
V(I8x16MinS) \
......@@ -2323,6 +2336,9 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I8x16SubSatU) \
V(I8x16RoundingAverageU) \
V(I8x16Swizzle) \
V(I8x16Shl) \
V(I8x16ShrS) \
V(I8x16ShrU) \
V(S128And) \
V(S128Or) \
V(S128Xor) \
......@@ -2338,6 +2354,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2ConvertLowI32x4S) \
V(F64x2ConvertLowI32x4U) \
V(F64x2PromoteLowF32x4) \
V(F64x2Splat) \
V(F32x4Abs) \
V(F32x4Neg) \
V(F32x4Sqrt) \
......@@ -2347,13 +2364,17 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Floor) \
V(F32x4Trunc) \
V(F32x4DemoteF64x2Zero) \
V(F32x4Splat) \
V(I64x2Abs) \
V(I64x2Neg) \
V(I64x2SConvertI32x4Low) \
V(I64x2SConvertI32x4High) \
V(I64x2UConvertI32x4Low) \
V(I64x2UConvertI32x4High) \
V(I64x2AllTrue) \
V(I64x2BitMask) \
V(I32x4Neg) \
V(I64x2Splat) \
V(I32x4Abs) \
V(I32x4SConvertF32x4) \
V(I32x4UConvertF32x4) \
......@@ -2365,48 +2386,28 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I32x4ExtAddPairwiseI16x8U) \
V(I32x4TruncSatF64x2SZero) \
V(I32x4TruncSatF64x2UZero) \
V(I32x4AllTrue) \
V(I32x4BitMask) \
V(I32x4Splat) \
V(I16x8Neg) \
V(I16x8Abs) \
V(I16x8AllTrue) \
V(I16x8BitMask) \
V(I16x8Splat) \
V(I8x16Neg) \
V(I8x16Abs) \
V(I8x16Popcnt) \
V(I8x16AllTrue) \
V(I8x16BitMask) \
V(I8x16Splat) \
V(I16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High) \
V(I16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High) \
V(I16x8ExtAddPairwiseI8x16S) \
V(I16x8ExtAddPairwiseI8x16U) \
V(S128Not)
#define SIMD_SHIFT_LIST(V) \
V(I64x2Shl) \
V(I64x2ShrS) \
V(I64x2ShrU) \
V(I32x4Shl) \
V(I32x4ShrS) \
V(I32x4ShrU) \
V(I16x8Shl) \
V(I16x8ShrS) \
V(I16x8ShrU) \
V(I8x16Shl) \
V(I8x16ShrS) \
V(I8x16ShrU)
#define SIMD_BOOL_LIST(V) \
V(V128AnyTrue) \
V(I64x2AllTrue) \
V(I32x4AllTrue) \
V(I16x8AllTrue) \
V(I8x16AllTrue)
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
PPCOperandGenerator g(this); \
Emit(kPPC_##Type##Splat, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0))); \
}
SIMD_TYPES(SIMD_VISIT_SPLAT)
#undef SIMD_VISIT_SPLAT
V(S128Not) \
V(V128AnyTrue)
#define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \
void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
......@@ -2439,11 +2440,10 @@ SIMD_TYPES(SIMD_VISIT_REPLACE_LANE)
#define SIMD_VISIT_BINOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register(), \
g.TempSimd128Register(), g.TempRegister()}; \
InstructionOperand temps[] = {g.TempRegister()}; \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
arraysize(temps), temps); \
}
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
......@@ -2452,41 +2452,18 @@ SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#define SIMD_VISIT_UNOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register()}; \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), arraysize(temps), temps); \
g.UseRegister(node->InputAt(0))); \
}
SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#undef SIMD_VISIT_UNOP
#undef SIMD_UNOP_LIST
#define SIMD_VISIT_SHIFT(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1))); \
}
SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT)
#undef SIMD_VISIT_SHIFT
#undef SIMD_SHIFT_LIST
#define SIMD_VISIT_BOOL(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0))); \
}
SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
#undef SIMD_VISIT_BOOL
#undef SIMD_BOOL_LIST
#define SIMD_VISIT_QFMOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
Emit(kPPC_##Opcode, g.DefineSameAsFirst(node), \
g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1)), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), \
g.UseRegister(node->InputAt(2))); \
}
SIMD_VISIT_QFMOP(F64x2Qfma)
......@@ -2495,32 +2472,6 @@ SIMD_VISIT_QFMOP(F32x4Qfma)
SIMD_VISIT_QFMOP(F32x4Qfms)
#undef SIMD_VISIT_QFMOP
#define SIMD_VISIT_BITMASK(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
InstructionOperand temps[] = {g.TempRegister()}; \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps); \
}
SIMD_VISIT_BITMASK(I8x16BitMask)
SIMD_VISIT_BITMASK(I16x8BitMask)
SIMD_VISIT_BITMASK(I32x4BitMask)
SIMD_VISIT_BITMASK(I64x2BitMask)
#undef SIMD_VISIT_BITMASK
#define SIMD_VISIT_PMIN_MAX(Type) \
void InstructionSelector::Visit##Type(Node* node) { \
PPCOperandGenerator g(this); \
Emit(kPPC_##Type, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); \
}
SIMD_VISIT_PMIN_MAX(F64x2Pmin)
SIMD_VISIT_PMIN_MAX(F32x4Pmin)
SIMD_VISIT_PMIN_MAX(F64x2Pmax)
SIMD_VISIT_PMIN_MAX(F32x4Pmax)
#undef SIMD_VISIT_PMIN_MAX
#undef SIMD_TYPES
#if V8_ENABLE_WEBASSEMBLY
void InstructionSelector::VisitI8x16Shuffle(Node* node) {
uint8_t shuffle[kSimd128Size];
......@@ -2539,8 +2490,8 @@ void InstructionSelector::VisitI8x16Shuffle(Node* node) {
? max_index - current_index
: total_lane_count - current_index + max_index);
}
Emit(kPPC_I8x16Shuffle, g.DefineAsRegister(node), g.UseUniqueRegister(input0),
g.UseUniqueRegister(input1),
Emit(kPPC_I8x16Shuffle, g.DefineAsRegister(node), g.UseRegister(input0),
g.UseRegister(input1),
g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped)),
g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 4)),
g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle_remapped + 8)),
......
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