PPC [simd]: Implement FP conversion on Sim

Change-Id: If9380a99318618199ced8f079d13ddee28cde770
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2745896Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73310}

src/codegen/ppc/constants-ppc.h

@@ -412,14 +412,6 @@ using Instr = uint32_t;
   V(xsrsqrtesp, XSRSQRTESP, 0xF0000028)                                      \
   /* VSX Scalar Square Root Single-Precision */                              \
   V(xssqrtsp, XSSQRTSP, 0xF000002C)                                          \
-  /* Move To VSR Doubleword */                                               \
-  V(mtvsrd, MTVSRD, 0x7C000166)                                              \
-  /* Move To VSR Double Doubleword */                                        \
-  V(mtvsrdd, MTVSRDD, 0x7C000366)                                            \
-  /* Move To VSR Word Algebraic */                                           \
-  V(mtvsrwa, MTVSRWA, 0x7C0001A6)                                            \
-  /* Move To VSR Word and Zero */                                            \
-  V(mtvsrwz, MTVSRWZ, 0x7C0001E6)                                            \
   /* VSX Scalar Absolute Value Double-Precision */                           \
   V(xsabsdp, XSABSDP, 0xF0000564)                                            \
   /* VSX Scalar Convert Double-Precision to Single-Precision */              \
@@ -1993,6 +1985,14 @@ using Instr = uint32_t;
   V(lxvdsx, LXVDSX, 0x7C000298)                            \
   /* Load VSR Vector Word*4 Indexed */                     \
   V(lxvw, LXVW, 0x7C000618)                                \
+  /* Move To VSR Doubleword */                             \
+  V(mtvsrd, MTVSRD, 0x7C000166)                            \
+  /* Move To VSR Double Doubleword */                      \
+  V(mtvsrdd, MTVSRDD, 0x7C000366)                          \
+  /* Move To VSR Word Algebraic */                         \
+  V(mtvsrwa, MTVSRWA, 0x7C0001A6)                          \
+  /* Move To VSR Word and Zero */                          \
+  V(mtvsrwz, MTVSRWZ, 0x7C0001E6)                          \
   /* Move From VSR Doubleword */                           \
   V(mfvsrd, MFVSRD, 0x7C000066)                            \
   /* Move From VSR Word and Zero */                        \
@@ -2935,10 +2935,14 @@ class Instruction {
       PPC_XL_OPCODE_LIST(OPCODE_CASES)
       PPC_XFL_OPCODE_LIST(OPCODE_CASES)
       PPC_XX1_OPCODE_LIST(OPCODE_CASES)
-      PPC_XX2_OPCODE_LIST(OPCODE_CASES)
       PPC_EVX_OPCODE_LIST(OPCODE_CASES)
       return static_cast<Opcode>(opcode);
     }
+    opcode = extcode | BitField(10, 2);
+    switch (opcode) {
+      PPC_XX2_OPCODE_LIST(OPCODE_CASES)
+      return static_cast<Opcode>(opcode);
+    }
     opcode = extcode | BitField(9, 1);
     switch (opcode) {
       PPC_XO_OPCODE_LIST(OPCODE_CASES)

src/execution/ppc/simulator-ppc.cc

@@ -1417,6 +1417,34 @@ void VectorCompareOp(Simulator* sim, Instruction* instr, bool is_fp,
   }
 }
 
+template <typename B, typename T>
+void VectorConverFromFPSaturate(Simulator* sim, Instruction* instr, B min_val,
+                                B max_val) {
+  int t = instr->RTValue();
+  int b = instr->RBValue();
+  FOR_EACH_LANE(i, float) {
+    B kMinVal = min_val;
+    B kMaxVal = max_val;
+    T t_val;
+    double b_val =
+        static_cast<double>(sim->get_simd_register_by_lane<float>(b, i));
+    if (isnan(b_val)) {
+      t_val = kMinVal;
+    } else {
+      // Round Towards Zero.
+      b_val = std::trunc(b_val);
+      if (b_val < kMinVal) {
+        t_val = kMinVal;
+      } else if (b_val > kMaxVal) {
+        t_val = kMaxVal;
+      } else {
+        t_val = static_cast<T>(b_val);
+      }
+    }
+    sim->set_simd_register_by_lane<T>(t, i, t_val);
+  }
+}
+
 template <typename T>
 T VSXFPMin(T x, T y) {
   // Handle +0 and -0.
@@ -4232,12 +4260,40 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
       break;
     }
 #undef VECTOR_COMPARE_OP
+    case XVCVSPSXWS: {
+      VectorConverFromFPSaturate<int64_t, int32_t>(this, instr, kMinInt,
+                                                   kMaxInt);
+      break;
+    }
+    case XVCVSPUXWS: {
+      VectorConverFromFPSaturate<uint64_t, uint32_t>(this, instr, 0,
+                                                     kMaxUInt32);
+      break;
+    }
+    case XVCVSXWSP: {
+      int t = instr->RTValue();
+      int b = instr->RBValue();
+      FOR_EACH_LANE(i, int32_t) {
+        int32_t b_val = get_simd_register_by_lane<int32_t>(b, i);
+        set_simd_register_by_lane<float>(t, i, static_cast<float>(b_val));
+      }
+      break;
+    }
+    case XVCVUXWSP: {
+      int t = instr->RTValue();
+      int b = instr->RBValue();
+      FOR_EACH_LANE(i, uint32_t) {
+        uint32_t b_val = get_simd_register_by_lane<uint32_t>(b, i);
+        set_simd_register_by_lane<float>(t, i, static_cast<float>(b_val));
+      }
+      break;
+    }
     case VSEL: {
       int vrt = instr->RTValue();
       int vra = instr->RAValue();
       int vrb = instr->RBValue();
       int vrc = instr->RCValue();
-      for (int i = 0; i < 2; i++) {
+      FOR_EACH_LANE(i, int64_t) {
         int64_t vra_val = get_simd_register_by_lane<int64_t>(vra, i);
         int64_t vrb_val = get_simd_register_by_lane<int64_t>(vrb, i);
         int64_t mask = get_simd_register_by_lane<int64_t>(vrc, i);