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Commit b973e235 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [liftoff]: add to Simd binary operations 

Adds Integer and FP Sub and Mull.

Change-Id: Ide2cfdbdc308d18011ba5cc6a61cd326c13c09b2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3048789Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75922}
parent 9999ac75
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Showing with 74 additions and 145 deletions
src/codegen/s390/macro-assembler-s390.cc
View file @ b973e235
......@@ -5216,7 +5216,17 @@ void TurboAssembler::I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
V(I64x2Add, va, 3) \
V(I32x4Add, va, 2) \
V(I16x8Add, va, 1) \
V(I8x16Add, va, 0)
V(I8x16Add, va, 0) \
V(F64x2Sub, vfs, 3) \
V(F32x4Sub, vfs, 2) \
V(I64x2Sub, vs, 3) \
V(I32x4Sub, vs, 2) \
V(I16x8Sub, vs, 1) \
V(I8x16Sub, vs, 0) \
V(F64x2Mul, vfm, 3) \
V(F32x4Mul, vfm, 2) \
V(I32x4Mul, vml, 2) \
V(I16x8Mul, vml, 1)
#define EMIT_SIMD_BINOP(name, op, condition) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src1, \
......@@ -5227,6 +5237,20 @@ SIMD_BINOP_LIST(EMIT_SIMD_BINOP)
#undef EMIT_SIMD_BINOP
#undef SIMD_BINOP_LIST
void TurboAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
Register scratch_1 = r0;
Register scratch_2 = r1;
for (int i = 0; i < 2; i++) {
vlgv(scratch_1, src1, MemOperand(r0, i), Condition(3));
vlgv(scratch_2, src2, MemOperand(r0, i), Condition(3));
MulS64(scratch_1, scratch_2);
scratch_1 = r1;
scratch_2 = ip;
}
vlvgp(dst, r0, r1);
}
} // namespace internal
} // namespace v8
......
src/codegen/s390/macro-assembler-s390.h
View file @ b973e235
......@@ -1066,18 +1066,31 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
Register src2, uint8_t imm_lane_idx);
void I8x16ReplaceLane(Simd128Register dst, Simd128Register src1,
Register src2, uint8_t imm_lane_idx);
void F64x2Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void F32x4Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I64x2Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I32x4Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I16x8Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
void I8x16Add(Simd128Register dst, Simd128Register src1,
Simd128Register src2);
#define SIMD_BINOP_LIST(V) \
V(F64x2Add) \
V(F32x4Add) \
V(I64x2Add) \
V(I32x4Add) \
V(I16x8Add) \
V(I8x16Add) \
V(F64x2Sub) \
V(F32x4Sub) \
V(I64x2Sub) \
V(I32x4Sub) \
V(I16x8Sub) \
V(I8x16Sub) \
V(F64x2Mul) \
V(F32x4Mul) \
V(I64x2Mul) \
V(I32x4Mul) \
V(I16x8Mul)
#define PROTOTYPE_SIMD_BINOP(name) \
void name(Simd128Register dst, Simd128Register src1, Simd128Register src2);
SIMD_BINOP_LIST(PROTOTYPE_SIMD_BINOP)
#undef PROTOTYPE_SIMD_BINOP
#undef SIMD_BINOP_LIST
// ---------------------------------------------------------------------------
// Pointer compression Support
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ b973e235
......@@ -2488,7 +2488,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(I64x2Add) \
V(I32x4Add) \
V(I16x8Add) \
V(I8x16Add)
V(I8x16Add) \
V(F64x2Sub) \
V(F32x4Sub) \
V(I64x2Sub) \
V(I32x4Sub) \
V(I16x8Sub) \
V(I8x16Sub) \
V(F64x2Mul) \
V(F32x4Mul) \
V(I64x2Mul) \
V(I32x4Mul) \
V(I16x8Mul)
#define EMIT_SIMD_BINOP(name) \
case kS390_##name: { \
......@@ -2554,18 +2565,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_REPLACE_LANE
#undef SIMD_REPLACE_LANE_LIST
// vector binops
case kS390_F64x2Sub: {
__ vfs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_F64x2Mul: {
__ vfm(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_F64x2Div: {
__ vfd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
......@@ -2600,18 +2599,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vfnms(dst, src1, src2, src0, Condition(3), Condition(0));
break;
}
case kS390_F32x4Sub: {
__ vfs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Mul: {
__ vfm(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Div: {
__ vfd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
......@@ -2646,57 +2633,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vfnms(dst, src1, src2, src0, Condition(2), Condition(0));
break;
}
case kS390_I64x2Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(3));
break;
}
case kS390_I64x2Mul: {
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Register scratch_0 = r0;
Register scratch_1 = r1;
for (int i = 0; i < 2; i++) {
__ vlgv(scratch_0, src0, MemOperand(r0, i), Condition(3));
__ vlgv(scratch_1, src1, MemOperand(r0, i), Condition(3));
__ MulS64(scratch_0, scratch_1);
scratch_0 = r1;
scratch_1 = ip;
}
__ vlvgp(i.OutputSimd128Register(), r0, r1);
break;
}
case kS390_I32x4Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I32x4Mul: {
__ vml(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(2));
break;
}
case kS390_I16x8Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(1));
break;
}
case kS390_I16x8Mul: {
__ vml(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(1));
break;
}
case kS390_I8x16Sub: {
__ vs(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
Condition(0));
break;
}
case kS390_I16x8RoundingAverageU: {
__ vavgl(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(0), Condition(0),
......
src/wasm/baseline/s390/liftoff-assembler-s390.h
View file @ b973e235
......@@ -2149,7 +2149,18 @@ void LiftoffAssembler::emit_smi_check(Register obj, Label* target,
V(i64x2_add, I64x2Add) \
V(i32x4_add, I32x4Add) \
V(i16x8_add, I16x8Add) \
V(i8x16_add, I8x16Add)
V(i8x16_add, I8x16Add) \
V(f64x2_sub, F64x2Sub) \
V(f32x4_sub, F32x4Sub) \
V(i64x2_sub, I64x2Sub) \
V(i32x4_sub, I32x4Sub) \
V(i16x8_sub, I16x8Sub) \
V(i8x16_sub, I8x16Sub) \
V(f64x2_mul, F64x2Mul) \
V(f32x4_mul, F32x4Mul) \
V(i64x2_mul, I64x2Mul) \
V(i32x4_mul, I32x4Mul) \
V(i16x8_mul, I16x8Mul)
#define EMIT_SIMD_BINOP(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
......@@ -2281,16 +2292,6 @@ bool LiftoffAssembler::emit_f64x2_nearest_int(LiftoffRegister dst,
return true;
}
void LiftoffAssembler::emit_f64x2_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2sub");
}
void LiftoffAssembler::emit_f64x2_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2mul");
}
void LiftoffAssembler::emit_f64x2_div(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f64x2div");
......@@ -2370,16 +2371,6 @@ bool LiftoffAssembler::emit_f32x4_nearest_int(LiftoffRegister dst,
return true;
}
void LiftoffAssembler::emit_f32x4_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4sub");
}
void LiftoffAssembler::emit_f32x4_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4mul");
}
void LiftoffAssembler::emit_f32x4_div(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_f32x4div");
......@@ -2447,16 +2438,6 @@ void LiftoffAssembler::emit_i64x2_shri_u(LiftoffRegister dst,
bailout(kSimd, "i64x2_shri_u");
}
void LiftoffAssembler::emit_i64x2_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i64x2sub");
}
void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i64x2mul");
}
void LiftoffAssembler::emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst,
LiftoffRegister src1,
LiftoffRegister src2) {
......@@ -2553,16 +2534,6 @@ void LiftoffAssembler::emit_i32x4_shri_u(LiftoffRegister dst,
bailout(kSimd, "i32x4_shri_u");
}
void LiftoffAssembler::emit_i32x4_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4sub");
}
void LiftoffAssembler::emit_i32x4_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i32x4mul");
}
void LiftoffAssembler::emit_i32x4_min_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
......@@ -2680,11 +2651,6 @@ void LiftoffAssembler::emit_i16x8_add_sat_s(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i16x8addsaturate_s");
}
void LiftoffAssembler::emit_i16x8_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8sub");
}
void LiftoffAssembler::emit_i16x8_sub_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
......@@ -2697,11 +2663,6 @@ void LiftoffAssembler::emit_i16x8_sub_sat_u(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i16x8subsaturate_u");
}
void LiftoffAssembler::emit_i16x8_mul(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8mul");
}
void LiftoffAssembler::emit_i16x8_add_sat_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
......@@ -2843,11 +2804,6 @@ void LiftoffAssembler::emit_i8x16_add_sat_s(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i8x16addsaturate_s");
}
void LiftoffAssembler::emit_i8x16_sub(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16sub");
}
void LiftoffAssembler::emit_i8x16_sub_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
......
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