s390x: rename Add/Sub operations

Change-Id: I232585076ecf6a824cdbe2e989eadaf96adcc1d8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2587241Reviewed-by: Milad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71737}

src/codegen/s390/macro-assembler-s390.h

@@ -175,59 +175,59 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   // Arithmetic Operations
 
   // Add (Register - Immediate)
-  void Add32(Register dst, const Operand& imm);
-  void AddP(Register dst, const Operand& imm);
-  void Add32(Register dst, Register src, const Operand& imm);
-  void AddP(Register dst, Register src, const Operand& imm);
+  void AddS32(Register dst, const Operand& imm);
+  void AddS64(Register dst, const Operand& imm);
+  void AddS32(Register dst, Register src, const Operand& imm);
+  void AddS64(Register dst, Register src, const Operand& imm);
 
   // Add (Register - Register)
-  void Add32(Register dst, Register src);
-  void AddP(Register dst, Register src);
-  void Add32(Register dst, Register src1, Register src2);
-  void AddP(Register dst, Register src1, Register src2);
+  void AddS32(Register dst, Register src);
+  void AddS64(Register dst, Register src);
+  void AddS32(Register dst, Register src1, Register src2);
+  void AddS64(Register dst, Register src1, Register src2);
 
   // Add (Register - Mem)
-  void Add32(Register dst, const MemOperand& opnd);
-  void AddP(Register dst, const MemOperand& opnd);
+  void AddS32(Register dst, const MemOperand& opnd);
+  void AddS64(Register dst, const MemOperand& opnd);
 
   // Add (Mem - Immediate)
-  void Add32(const MemOperand& opnd, const Operand& imm);
-  void AddP(const MemOperand& opnd, const Operand& imm);
+  void AddS32(const MemOperand& opnd, const Operand& imm);
+  void AddS64(const MemOperand& opnd, const Operand& imm);
 
   // Add Logical (Register - Register)
-  void AddLogical32(Register dst, Register src1, Register src2);
+  void AddU32(Register dst, Register src1, Register src2);
 
   // Add Logical (Register - Immediate)
-  void AddLogical(Register dst, const Operand& imm);
-  void AddLogicalP(Register dst, const Operand& imm);
+  void AddU32(Register dst, const Operand& imm);
+  void AddU64(Register dst, const Operand& imm);
 
   // Add Logical (Register - Mem)
-  void AddLogical(Register dst, const MemOperand& opnd);
-  void AddLogicalP(Register dst, const MemOperand& opnd);
+  void AddU32(Register dst, const MemOperand& opnd);
+  void AddU64(Register dst, const MemOperand& opnd);
 
   // Subtract (Register - Immediate)
-  void Sub32(Register dst, const Operand& imm);
-  void SubP(Register dst, const Operand& imm);
-  void Sub32(Register dst, Register src, const Operand& imm);
-  void SubP(Register dst, Register src, const Operand& imm);
+  void SubS32(Register dst, const Operand& imm);
+  void SubS64(Register dst, const Operand& imm);
+  void SubS32(Register dst, Register src, const Operand& imm);
+  void SubS64(Register dst, Register src, const Operand& imm);
 
   // Subtract (Register - Register)
-  void Sub32(Register dst, Register src);
-  void SubP(Register dst, Register src);
-  void Sub32(Register dst, Register src1, Register src2);
-  void SubP(Register dst, Register src1, Register src2);
+  void SubS32(Register dst, Register src);
+  void SubS64(Register dst, Register src);
+  void SubS32(Register dst, Register src1, Register src2);
+  void SubS64(Register dst, Register src1, Register src2);
 
   // Subtract (Register - Mem)
-  void Sub32(Register dst, const MemOperand& opnd);
-  void SubP(Register dst, const MemOperand& opnd);
+  void SubS32(Register dst, const MemOperand& opnd);
+  void SubS64(Register dst, const MemOperand& opnd);
   void LoadAndSub32(Register dst, Register src, const MemOperand& opnd);
   void LoadAndSub64(Register dst, Register src, const MemOperand& opnd);
 
   // Subtract Logical (Register - Mem)
-  void SubLogical(Register dst, const MemOperand& opnd);
-  void SubLogicalP(Register dst, const MemOperand& opnd);
+  void SubU32(Register dst, const MemOperand& opnd);
+  void SubU64(Register dst, const MemOperand& opnd);
   // Subtract Logical 32-bit
-  void SubLogical32(Register dst, Register src1, Register src2);
+  void SubU32(Register dst, Register src1, Register src2);
 
   // Multiply
   void MulP(Register dst, const Operand& opnd);

src/compiler/backend/s390/code-generator-s390.cc

@@ -210,10 +210,10 @@ class OutOfLineRecordWrite final : public OutOfLineCode {
                      MemoryChunk::kPointersToHereAreInterestingMask, eq,
                      exit());
     if (offset_ == no_reg) {
-      __ AddP(scratch1_, object_, Operand(offset_immediate_));
+      __ AddS64(scratch1_, object_, Operand(offset_immediate_));
     } else {
       DCHECK_EQ(0, offset_immediate_);
-      __ AddP(scratch1_, object_, offset_);
+      __ AddS64(scratch1_, object_, offset_);
     }
     RememberedSetAction const remembered_set_action =
         mode_ > RecordWriteMode::kValueIsMap ? EMIT_REMEMBERED_SET
@@ -290,7 +290,7 @@ Condition FlagsConditionToCondition(FlagsCondition condition, ArchOpcode op) {
     case kSignedGreaterThan:
       return gt;
     case kOverflow:
-      // Overflow checked for AddP/SubP only.
+      // Overflow checked for AddS64/SubS64 only.
       switch (op) {
         case kS390_Add32:
         case kS390_Add64:
@@ -1064,13 +1064,13 @@ void AdjustStackPointerForTailCall(
     if (pending_pushes != nullptr) {
       FlushPendingPushRegisters(tasm, state, pending_pushes);
     }
-    tasm->AddP(sp, sp, Operand(-stack_slot_delta * kSystemPointerSize));
+    tasm->AddS64(sp, sp, Operand(-stack_slot_delta * kSystemPointerSize));
     state->IncreaseSPDelta(stack_slot_delta);
   } else if (allow_shrinkage && stack_slot_delta < 0) {
     if (pending_pushes != nullptr) {
       FlushPendingPushRegisters(tasm, state, pending_pushes);
     }
-    tasm->AddP(sp, sp, Operand(-stack_slot_delta * kSystemPointerSize));
+    tasm->AddS64(sp, sp, Operand(-stack_slot_delta * kSystemPointerSize));
     state->IncreaseSPDelta(stack_slot_delta);
   }
 }
@@ -1436,7 +1436,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
 
       if (ShouldApplyOffsetToStackCheck(instr, &offset)) {
         lhs_register = i.TempRegister(0);
-        __ SubP(lhs_register, sp, Operand(offset));
+        __ SubS64(lhs_register, sp, Operand(offset));
       }
 
       constexpr size_t kValueIndex = 0;
@@ -1486,8 +1486,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kArchStackSlot: {
       FrameOffset offset =
           frame_access_state()->GetFrameOffset(i.InputInt32(0));
-      __ AddP(i.OutputRegister(), offset.from_stack_pointer() ? sp : fp,
-              Operand(offset.offset()));
+      __ AddS64(i.OutputRegister(), offset.from_stack_pointer() ? sp : fp,
+                Operand(offset.offset()));
       break;
     }
     case kArchWordPoisonOnSpeculation:
@@ -1676,15 +1676,15 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kS390_Add32: {
       // zero-ext
       if (CpuFeatures::IsSupported(DISTINCT_OPS)) {
-        ASSEMBLE_BIN32_OP(RRRInstr(ark), RM32Instr(Add32), RRIInstr(Add32));
+        ASSEMBLE_BIN32_OP(RRRInstr(ark), RM32Instr(AddS32), RRIInstr(AddS32));
       } else {
-        ASSEMBLE_BIN32_OP(RRInstr(ar), RM32Instr(Add32), RIInstr(Add32));
+        ASSEMBLE_BIN32_OP(RRInstr(ar), RM32Instr(AddS32), RIInstr(AddS32));
       }
       break;
     }
     case kS390_Add64:
       if (CpuFeatures::IsSupported(DISTINCT_OPS)) {
-        ASSEMBLE_BIN_OP(RRRInstr(agrk), RM64Instr(ag), RRIInstr(AddP));
+        ASSEMBLE_BIN_OP(RRRInstr(agrk), RM64Instr(ag), RRIInstr(AddS64));
       } else {
         ASSEMBLE_BIN_OP(RRInstr(agr), RM64Instr(ag), RIInstr(agfi));
       }
@@ -1698,16 +1698,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kS390_Sub32:
       // zero-ext
       if (CpuFeatures::IsSupported(DISTINCT_OPS)) {
-        ASSEMBLE_BIN32_OP(RRRInstr(srk), RM32Instr(Sub32), RRIInstr(Sub32));
+        ASSEMBLE_BIN32_OP(RRRInstr(srk), RM32Instr(SubS32), RRIInstr(SubS32));
       } else {
-        ASSEMBLE_BIN32_OP(RRInstr(sr), RM32Instr(Sub32), RIInstr(Sub32));
+        ASSEMBLE_BIN32_OP(RRInstr(sr), RM32Instr(SubS32), RIInstr(SubS32));
       }
       break;
     case kS390_Sub64:
       if (CpuFeatures::IsSupported(DISTINCT_OPS)) {
-        ASSEMBLE_BIN_OP(RRRInstr(sgrk), RM64Instr(sg), RRIInstr(SubP));
+        ASSEMBLE_BIN_OP(RRRInstr(sgrk), RM64Instr(sg), RRIInstr(SubS64));
       } else {
-        ASSEMBLE_BIN_OP(RRInstr(sgr), RM64Instr(sg), RIInstr(SubP));
+        ASSEMBLE_BIN_OP(RRInstr(sgr), RM64Instr(sg), RIInstr(SubS64));
       }
       break;
     case kS390_SubFloat:
@@ -1924,7 +1924,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     case kS390_Cntlz32: {
       __ llgfr(i.OutputRegister(), i.InputRegister(0));
       __ flogr(r0, i.OutputRegister());
-      __ Add32(i.OutputRegister(), r0, Operand(-32));
+      __ AddS32(i.OutputRegister(), r0, Operand(-32));
       // No need to zero-ext b/c llgfr is done already
       break;
     }
@@ -2608,8 +2608,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                                 true);                                       \
     });                                                                      \
     break;
-      ATOMIC_BINOP_CASE(Add, Add32)
-      ATOMIC_BINOP_CASE(Sub, Sub32)
+      ATOMIC_BINOP_CASE(Add, AddS32)
+      ATOMIC_BINOP_CASE(Sub, SubS32)
       ATOMIC_BINOP_CASE(And, And)
       ATOMIC_BINOP_CASE(Or, Or)
       ATOMIC_BINOP_CASE(Xor, Xor)
@@ -4417,7 +4417,8 @@ void CodeGenerator::AssembleConstructFrame() {
             FieldMemOperand(kWasmInstanceRegister,
                             WasmInstanceObject::kRealStackLimitAddressOffset));
         __ LoadP(scratch, MemOperand(scratch));
-        __ AddP(scratch, scratch, Operand(required_slots * kSystemPointerSize));
+        __ AddS64(scratch, scratch,
+                  Operand(required_slots * kSystemPointerSize));
         __ CmpLogicalP(sp, scratch);
         __ bge(&done);
       }
@@ -4536,7 +4537,7 @@ void CodeGenerator::AssembleReturn(InstructionOperand* additional_pop_count) {
   if (drop_jsargs) {
     // We must pop all arguments from the stack (including the receiver). This
     // number of arguments is given by max(1 + argc_reg, parameter_count).
-    __ AddP(argc_reg, argc_reg, Operand(1));  // Also pop the receiver.
+    __ AddS64(argc_reg, argc_reg, Operand(1));  // Also pop the receiver.
     if (parameter_count > 1) {
       Label skip;
       __ CmpP(argc_reg, Operand(parameter_count));

src/compiler/backend/s390/instruction-selector-s390.cc

@@ -728,8 +728,8 @@ static void VisitGeneralStore(
     InstructionOperand inputs[3];
     size_t input_count = 0;
     inputs[input_count++] = g.UseUniqueRegister(base);
-    // OutOfLineRecordWrite uses the offset in an 'AddP' instruction as well as
-    // for the store itself, so we must check compatibility with both.
+    // OutOfLineRecordWrite uses the offset in an 'AddS64' instruction as well
+    // as for the store itself, so we must check compatibility with both.
     if (g.CanBeImmediate(offset, OperandMode::kInt20Imm)) {
       inputs[input_count++] = g.UseImmediate(offset);
       addressing_mode = kMode_MRI;

src/wasm/baseline/s390/liftoff-assembler-s390.h

@@ -306,8 +306,8 @@ void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) {
     // Use r3 for start address (inclusive), r4 for end address (exclusive).
     push(r3);
     push(r4);
-    SubP(r3, fp, Operand(start + size));
-    SubP(r4, fp, Operand(start));
+    SubS64(r3, fp, Operand(start + size));
+    SubS64(r4, fp, Operand(start));
 
     Label loop;
     bind(&loop);