[loong64] Fix the wrong encoding and usage of maskeqz/masknez instructions

Change-Id: Ie08574da9b2192aa250e2cbc0efaf049c6e9026a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3354670Reviewed-by: Yu Liu <liuyu@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/main@{#78439}

src/codegen/loong64/constants-loong64.h

@@ -337,8 +337,8 @@ enum Opcode : uint32_t {
   SUB_D = 0x23U << 15,
   SLT = 0x24U << 15,
   SLTU = 0x25U << 15,
-  MASKNEZ = 0x26U << 15,
-  MASKEQZ = 0x27U << 15,
+  MASKEQZ = 0x26U << 15,
+  MASKNEZ = 0x27U << 15,
   NOR = 0x28U << 15,
   AND = 0x29U << 15,
   OR = 0x2aU << 15,

src/codegen/loong64/macro-assembler-loong64.cc

@@ -1938,16 +1938,16 @@ void TurboAssembler::Move(FPURegister dst, uint64_t src) {
 void TurboAssembler::Movz(Register rd, Register rj, Register rk) {
   UseScratchRegisterScope temps(this);
   Register scratch = temps.Acquire();
-  maskeqz(scratch, rj, rk);
-  masknez(rd, rd, rk);
+  masknez(scratch, rj, rk);
+  maskeqz(rd, rd, rk);
   or_(rd, rd, scratch);
 }
 
 void TurboAssembler::Movn(Register rd, Register rj, Register rk) {
   UseScratchRegisterScope temps(this);
   Register scratch = temps.Acquire();
-  masknez(scratch, rj, rk);
-  maskeqz(rd, rd, rk);
+  maskeqz(scratch, rj, rk);
+  masknez(rd, rd, rk);
   or_(rd, rd, scratch);
 }
 
@@ -2037,12 +2037,12 @@ void TurboAssembler::LoadZeroOnCondition(Register rd, Register rj,
 
 void TurboAssembler::LoadZeroIfConditionNotZero(Register dest,
                                                 Register condition) {
-  maskeqz(dest, dest, condition);
+  masknez(dest, dest, condition);
 }
 
 void TurboAssembler::LoadZeroIfConditionZero(Register dest,
                                              Register condition) {
-  masknez(dest, dest, condition);
+  maskeqz(dest, dest, condition);
 }
 
 void TurboAssembler::LoadZeroIfFPUCondition(Register dest, CFRegister cc) {

src/compiler/backend/loong64/code-generator-loong64.cc

@@ -962,11 +962,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kLoong64Div_w:
       __ Div_w(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
-      __ masknez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
+      __ maskeqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       break;
     case kLoong64Div_wu:
       __ Div_wu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
-      __ masknez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
+      __ maskeqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       break;
     case kLoong64Mod_w:
       __ Mod_w(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
@@ -979,11 +979,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kLoong64Div_d:
       __ Div_d(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
-      __ masknez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
+      __ maskeqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       break;
     case kLoong64Div_du:
       __ Div_du(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
-      __ masknez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
+      __ maskeqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       break;
     case kLoong64Mod_d:
       __ Mod_d(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));

src/execution/loong64/simulator-loong64.cc

@@ -3484,13 +3484,13 @@ void Simulator::DecodeTypeOp17() {
       printf_instr("MASKEQZ\t %s: %016lx, %s, %016lx, %s, %016lx\n",
                    Registers::Name(rd_reg()), rd(), Registers::Name(rj_reg()),
                    rj(), Registers::Name(rk_reg()), rk());
-      SetResult(rd_reg(), rk() == 0 ? rj() : 0);
+      SetResult(rd_reg(), rk() == 0 ? 0 : rj());
       break;
     case MASKNEZ:
       printf_instr("MASKNEZ\t %s: %016lx, %s, %016lx, %s, %016lx\n",
                    Registers::Name(rd_reg()), rd(), Registers::Name(rj_reg()),
                    rj(), Registers::Name(rk_reg()), rk());
-      SetResult(rd_reg(), rk() != 0 ? rj() : 0);
+      SetResult(rd_reg(), rk() != 0 ? 0 : rj());
       break;
     case NOR:
       printf_instr("NOR\t %s: %016lx, %s, %016lx, %s, %016lx\n",

test/cctest/test-assembler-loong64.cc

@@ -1546,10 +1546,10 @@ TEST(LA11) {
   CHECK_EQ(static_cast<int64_t>(0x81a15c3000), t.result_bstrins_d_si2);
   CHECK_EQ(static_cast<int64_t>(0x1e), t.result_bstrpick_d_si1);
   CHECK_EQ(static_cast<int64_t>(0xfb80), t.result_bstrpick_d_si2);
-  CHECK_EQ(static_cast<int64_t>(0), t.result_maskeqz_si1);
-  CHECK_EQ(static_cast<int64_t>(0xFB8017FF781A15C3), t.result_maskeqz_si2);
-  CHECK_EQ(static_cast<int64_t>(0x10C021098B710CDE), t.result_masknez_si1);
-  CHECK_EQ(static_cast<int64_t>(0), t.result_masknez_si2);
+  CHECK_EQ(static_cast<int64_t>(0x10C021098B710CDE), t.result_maskeqz_si1);
+  CHECK_EQ(static_cast<int64_t>(0), t.result_maskeqz_si2);
+  CHECK_EQ(static_cast<int64_t>(0), t.result_masknez_si1);
+  CHECK_EQ(static_cast<int64_t>(0xFB8017FF781A15C3), t.result_masknez_si2);
 }
 
 uint64_t run_beq(int64_t value1, int64_t value2, int16_t offset) {

test/cctest/test-disasm-loong64.cc

@@ -621,11 +621,11 @@ TEST(TypeOp17) {
   COMPARE(slt(a5, a5, a6), "00122929       slt          a5, a5, a6");
   COMPARE(slt(a6, t3, t4), "001241ea       slt          a6, t3, t4");
 
-  COMPARE(masknez(a5, a5, a3), "00131d29       masknez      a5, a5, a3");
-  COMPARE(masknez(a3, a4, a5), "00132507       masknez      a3, a4, a5");
+  COMPARE(maskeqz(a6, a7, t0), "0013316a       maskeqz      a6, a7, t0");
+  COMPARE(maskeqz(t1, t2, t3), "00133dcd       maskeqz      t1, t2, t3");
 
-  COMPARE(maskeqz(a6, a7, t0), "0013b16a       maskeqz      a6, a7, t0");
-  COMPARE(maskeqz(t1, t2, t3), "0013bdcd       maskeqz      t1, t2, t3");
+  COMPARE(masknez(a5, a5, a3), "00139d29       masknez      a5, a5, a3");
+  COMPARE(masknez(a3, a4, a5), "0013a507       masknez      a3, a4, a5");
 
   COMPARE(or_(s3, sp, zero_reg),
           "0015007a       or           s3, sp, zero_reg");