PPC: Fix LoadU64WithUpdate in macro assembler

`ldu` requires offset to be 4 byte aligned.
Moving it under `GenerateMemoryOperationWithAlign`.

Change-Id: I9f15a3e4d04f5381d0fb74abdd2f4d9160bc7243
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3629345Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#80380}

src/codegen/ppc/macro-assembler-ppc.cc

@@ -3231,8 +3231,9 @@ void MacroAssembler::AndSmiLiteral(Register dst, Register src, Smi smi,
   }
 
 #define MEM_OP_WITH_ALIGN_LIST(V) \
-  V(LoadU64, ld, ldx)             \
   V(LoadS32, lwa, lwax)           \
+  V(LoadU64, ld, ldx)             \
+  V(LoadU64WithUpdate, ldu, ldux) \
   V(StoreU64, std, stdx)          \
   V(StoreU64WithUpdate, stdu, stdux)
 
@@ -3257,7 +3258,6 @@ MEM_OP_WITH_ALIGN_LIST(MEM_OP_WITH_ALIGN_FUNCTION)
   V(LoadF32, DoubleRegister, lfs, lfsx)                \
   V(StoreF64, DoubleRegister, stfd, stfdx)             \
   V(StoreF32, DoubleRegister, stfs, stfsx)             \
-  V(LoadU64WithUpdate, Register, ldu, ldux)            \
   V(LoadF64WithUpdate, DoubleRegister, lfdu, lfdux)    \
   V(LoadF32WithUpdate, DoubleRegister, lfsu, lfsux)    \
   V(StoreF64WithUpdate, DoubleRegister, stfdu, stfdux) \