Commit b14b3d93 authored by Junliang Yan's avatar Junliang Yan Committed by V8 LUCI CQ

ppc: cleanup And/Or/Xor macros

Change-Id: I643bca82ee86d15e6cc65ab8856fb8b4bf5fd8e2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3038247Reviewed-by: 's avatarMilad Fa <mfarazma@redhat.com>
Commit-Queue: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75791}
parent 62c83291
......@@ -2746,7 +2746,7 @@ void TurboAssembler::AndU64(Register dst, Register src, Register value,
void TurboAssembler::OrU64(Register dst, Register src, const Operand& value,
Register scratch, RCBit r) {
if (is_int16(value.immediate()) && r == SetRC) {
if (is_int16(value.immediate()) && r == LeaveRC) {
ori(dst, src, value);
} else {
mov(scratch, value);
......@@ -2761,7 +2761,7 @@ void TurboAssembler::OrU64(Register dst, Register src, Register value,
void TurboAssembler::XorU64(Register dst, Register src, const Operand& value,
Register scratch, RCBit r) {
if (is_int16(value.immediate()) && r == SetRC) {
if (is_int16(value.immediate()) && r == LeaveRC) {
xori(dst, src, value);
} else {
mov(scratch, value);
......@@ -2870,56 +2870,6 @@ void TurboAssembler::CmpU32(Register src1, Register src2, CRegister cr) {
cmplw(src1, src2, cr);
}
void MacroAssembler::And(Register ra, Register rs, const Operand& rb,
RCBit rc) {
if (rb.is_reg()) {
and_(ra, rs, rb.rm(), rc);
} else {
if (is_uint16(rb.immediate()) && RelocInfo::IsNone(rb.rmode_) &&
rc == SetRC) {
andi(ra, rs, rb);
} else {
// mov handles the relocation.
DCHECK(rs != r0);
mov(r0, rb);
and_(ra, rs, r0, rc);
}
}
}
void MacroAssembler::Or(Register ra, Register rs, const Operand& rb, RCBit rc) {
if (rb.is_reg()) {
orx(ra, rs, rb.rm(), rc);
} else {
if (is_uint16(rb.immediate()) && RelocInfo::IsNone(rb.rmode_) &&
rc == LeaveRC) {
ori(ra, rs, rb);
} else {
// mov handles the relocation.
DCHECK(rs != r0);
mov(r0, rb);
orx(ra, rs, r0, rc);
}
}
}
void MacroAssembler::Xor(Register ra, Register rs, const Operand& rb,
RCBit rc) {
if (rb.is_reg()) {
xor_(ra, rs, rb.rm(), rc);
} else {
if (is_uint16(rb.immediate()) && RelocInfo::IsNone(rb.rmode_) &&
rc == LeaveRC) {
xori(ra, rs, rb);
} else {
// mov handles the relocation.
DCHECK(rs != r0);
mov(r0, rb);
xor_(ra, rs, r0, rc);
}
}
}
void MacroAssembler::CmpSmiLiteral(Register src1, Smi smi, Register scratch,
CRegister cr) {
#if defined(V8_COMPRESS_POINTERS) || defined(V8_31BIT_SMIS_ON_64BIT_ARCH)
......
......@@ -203,19 +203,19 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
void AndU64(Register dst, Register src, Register value, RCBit r = SetRC);
void OrU64(Register dst, Register src, const Operand& value,
Register scratch = r0, RCBit r = SetRC);
void OrU64(Register dst, Register src, Register value, RCBit r = SetRC);
void OrU64(Register dst, Register src, Register value, RCBit r = LeaveRC);
void XorU64(Register dst, Register src, const Operand& value,
Register scratch = r0, RCBit r = SetRC);
void XorU64(Register dst, Register src, Register value, RCBit r = SetRC);
void XorU64(Register dst, Register src, Register value, RCBit r = LeaveRC);
void AndU32(Register dst, Register src, const Operand& value,
Register scratch = r0, RCBit r = SetRC);
void AndU32(Register dst, Register src, Register value, RCBit r = SetRC);
void OrU32(Register dst, Register src, const Operand& value,
Register scratch = r0, RCBit r = SetRC);
void OrU32(Register dst, Register src, Register value, RCBit r = SetRC);
void OrU32(Register dst, Register src, Register value, RCBit r = LeaveRC);
void XorU32(Register dst, Register src, const Operand& value,
Register scratch = r0, RCBit r = SetRC);
void XorU32(Register dst, Register src, Register value, RCBit r = SetRC);
void XorU32(Register dst, Register src, Register value, RCBit r = LeaveRC);
void Push(Register src) { push(src); }
// Push a handle.
......@@ -861,10 +861,6 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
// load a literal double value <value> to FPR <result>
void And(Register ra, Register rs, const Operand& rb, RCBit rc = LeaveRC);
void Or(Register ra, Register rs, const Operand& rb, RCBit rc = LeaveRC);
void Xor(Register ra, Register rs, const Operand& rb, RCBit rc = LeaveRC);
void AddSmiLiteral(Register dst, Register src, Smi smi, Register scratch);
void SubSmiLiteral(Register dst, Register src, Smi smi, Register scratch);
void CmpSmiLiteral(Register src1, Smi smi, Register scratch,
......
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