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Commit b06075df authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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s390: [wasm-simd] Implement simd Splat, ExtractLane and ReplaceLane 

Change-Id: I2b75df9c6189007d8b3aace631a8b403663500a3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1970251Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#65586}
parent 338799cd
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Showing with 178 additions and 32 deletions
src/compiler/backend/s390/code-generator-s390.cc
View file @ b06075df
......@@ -2884,6 +2884,109 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_Word64AtomicCompareExchangeUint64:
ASSEMBLE_ATOMIC64_COMP_EXCHANGE_WORD64();
break;
// vector replicate element
case kS390_F32x4Splat: {
#ifdef V8_TARGET_BIG_ENDIAN
__ vrep(i.OutputSimd128Register(), i.InputDoubleRegister(0), Operand(0),
Condition(2));
#else
__ vrep(i.OutputSimd128Register(), i.InputDoubleRegister(0), Operand(1),
Condition(2));
#endif
break;
}
case kS390_I32x4Splat: {
Simd128Register dst = i.OutputSimd128Register();
__ vlvg(dst, i.InputRegister(0), MemOperand(r0, 0), Condition(2));
__ vrep(dst, dst, Operand(0), Condition(2));
break;
}
case kS390_I16x8Splat: {
Simd128Register dst = i.OutputSimd128Register();
__ vlvg(dst, i.InputRegister(0), MemOperand(r0, 0), Condition(1));
__ vrep(dst, dst, Operand(0), Condition(1));
break;
}
case kS390_I8x16Splat: {
Simd128Register dst = i.OutputSimd128Register();
__ vlvg(dst, i.InputRegister(0), MemOperand(r0, 0), Condition(0));
__ vrep(dst, dst, Operand(0), Condition(0));
break;
}
// vector extract element
case kS390_F32x4ExtractLane: {
__ vrep(i.OutputDoubleRegister(), i.InputSimd128Register(0),
Operand(3 - i.InputInt8(1)), Condition(2));
break;
}
case kS390_I32x4ExtractLane: {
__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
MemOperand(r0, 3 - i.InputInt8(1)), Condition(2));
break;
}
case kS390_I16x8ExtractLaneU: {
__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
MemOperand(r0, 7 - i.InputInt8(1)), Condition(1));
break;
}
case kS390_I16x8ExtractLaneS: {
__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
MemOperand(r0, 7 - i.InputInt8(1)), Condition(1));
break;
}
case kS390_I8x16ExtractLaneU: {
__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
MemOperand(r0, 15 - i.InputInt8(1)), Condition(0));
break;
}
case kS390_I8x16ExtractLaneS: {
__ vlgv(i.OutputRegister(), i.InputSimd128Register(0),
MemOperand(r0, 15 - i.InputInt8(1)), Condition(0));
break;
}
// vector replace element
case kS390_F32x4ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ lgdr(kScratchReg, i.InputDoubleRegister(2));
__ srlg(kScratchReg, kScratchReg, Operand(32));
__ vlvg(i.OutputSimd128Register(), kScratchReg,
MemOperand(r0, 3 - i.InputInt8(1)), Condition(2));
break;
}
case kS390_I32x4ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(i.OutputSimd128Register(), i.InputRegister(2),
MemOperand(r0, 3 - i.InputInt8(1)), Condition(2));
break;
}
case kS390_I16x8ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(i.OutputSimd128Register(), i.InputRegister(2),
MemOperand(r0, 7 - i.InputInt8(1)), Condition(1));
break;
}
case kS390_I8x16ReplaceLane: {
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ vlr(dst, src, Condition(0), Condition(0), Condition(0));
}
__ vlvg(i.OutputSimd128Register(), i.InputRegister(2),
MemOperand(r0, 15 - i.InputInt8(1)), Condition(0));
break;
}
// vector binops
case kS390_F32x4Add: {
__ vfa(i.OutputSimd128Register(), i.InputSimd128Register(0),
......
src/compiler/backend/s390/instruction-codes-s390.h
View file @ b06075df
......@@ -197,18 +197,32 @@ namespace compiler {
V(S390_Word64AtomicXorUint16) \
V(S390_Word64AtomicXorUint32) \
V(S390_Word64AtomicXorUint64) \
V(S390_F32x4Splat) \
V(S390_F32x4ExtractLane) \
V(S390_F32x4ReplaceLane) \
V(S390_F32x4Add) \
V(S390_F32x4AddHoriz) \
V(S390_F32x4Sub) \
V(S390_F32x4Mul) \
V(S390_I32x4Splat) \
V(S390_I32x4ExtractLane) \
V(S390_I32x4ReplaceLane) \
V(S390_I32x4Add) \
V(S390_I32x4AddHoriz) \
V(S390_I32x4Sub) \
V(S390_I32x4Mul) \
V(S390_I16x8Splat) \
V(S390_I16x8ExtractLaneU) \
V(S390_I16x8ExtractLaneS) \
V(S390_I16x8ReplaceLane) \
V(S390_I16x8Add) \
V(S390_I16x8AddHoriz) \
V(S390_I16x8Sub) \
V(S390_I16x8Mul) \
V(S390_I8x16Splat) \
V(S390_I8x16ExtractLaneU) \
V(S390_I8x16ExtractLaneS) \
V(S390_I8x16ReplaceLane) \
V(S390_I8x16Add) \
V(S390_I8x16Sub) \
V(S390_I8x16Mul) \
......
src/compiler/backend/s390/instruction-scheduler-s390.cc
View file @ b06075df
......@@ -143,18 +143,32 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kS390_CompressSigned:
case kS390_CompressPointer:
case kS390_CompressAny:
case kS390_F32x4Splat:
case kS390_F32x4ExtractLane:
case kS390_F32x4ReplaceLane:
case kS390_F32x4Add:
case kS390_F32x4AddHoriz:
case kS390_F32x4Sub:
case kS390_F32x4Mul:
case kS390_I32x4Splat:
case kS390_I32x4ExtractLane:
case kS390_I32x4ReplaceLane:
case kS390_I32x4Add:
case kS390_I32x4AddHoriz:
case kS390_I32x4Sub:
case kS390_I32x4Mul:
case kS390_I16x8Splat:
case kS390_I16x8ExtractLaneU:
case kS390_I16x8ExtractLaneS:
case kS390_I16x8ReplaceLane:
case kS390_I16x8Add:
case kS390_I16x8AddHoriz:
case kS390_I16x8Sub:
case kS390_I16x8Mul:
case kS390_I8x16Splat:
case kS390_I8x16ExtractLaneU:
case kS390_I8x16ExtractLaneS:
case kS390_I8x16ReplaceLane:
case kS390_I8x16Add:
case kS390_I8x16Sub:
case kS390_I8x16Mul:
......
src/compiler/backend/s390/instruction-selector-s390.cc
View file @ b06075df
......@@ -2515,18 +2515,11 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
VisitGeneralStore(this, node, rep);
}
#define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \
void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
UNIMPLEMENTED(); \
}
SIMD_VISIT_EXTRACT_LANE(F64x2, )
SIMD_VISIT_EXTRACT_LANE(F32x4, )
SIMD_VISIT_EXTRACT_LANE(I32x4, )
SIMD_VISIT_EXTRACT_LANE(I16x8, U)
SIMD_VISIT_EXTRACT_LANE(I16x8, S)
SIMD_VISIT_EXTRACT_LANE(I8x16, U)
SIMD_VISIT_EXTRACT_LANE(I8x16, S)
#undef SIMD_VISIT_EXTRACT_LANE
#define SIMD_TYPES(V) \
V(F32x4) \
V(I32x4) \
V(I16x8) \
V(I8x16)
#define SIMD_BINOP_LIST(V) \
V(F32x4Add) \
......@@ -2545,22 +2538,54 @@ SIMD_VISIT_EXTRACT_LANE(I8x16, S)
V(I8x16Sub) \
V(I8x16Mul)
#define VISIT_SIMD_BINOP(Opcode) \
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
S390OperandGenerator g(this); \
Emit(kS390_##Type##Splat, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0))); \
}
SIMD_TYPES(SIMD_VISIT_SPLAT)
#undef SIMD_VISIT_SPLAT
#define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \
void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \
S390OperandGenerator g(this); \
int32_t lane = OpParameter<int32_t>(node->op()); \
Emit(kS390_##Type##ExtractLane##Sign, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane)); \
}
SIMD_VISIT_EXTRACT_LANE(F32x4, )
SIMD_VISIT_EXTRACT_LANE(I32x4, )
SIMD_VISIT_EXTRACT_LANE(I16x8, U)
SIMD_VISIT_EXTRACT_LANE(I16x8, S)
SIMD_VISIT_EXTRACT_LANE(I8x16, U)
SIMD_VISIT_EXTRACT_LANE(I8x16, S)
#undef SIMD_VISIT_EXTRACT_LANE
#define SIMD_VISIT_REPLACE_LANE(Type) \
void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
S390OperandGenerator g(this); \
int32_t lane = OpParameter<int32_t>(node->op()); \
Emit(kS390_##Type##ReplaceLane, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), g.UseImmediate(lane), \
g.UseRegister(node->InputAt(1))); \
}
SIMD_TYPES(SIMD_VISIT_REPLACE_LANE)
#undef SIMD_VISIT_REPLACE_LANE
#define SIMD_VISIT_BINOP(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
S390OperandGenerator g(this); \
InstructionOperand temps[] = {g.TempSimd128Register(), \
g.TempSimd128Register()}; \
Emit(kS390_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(0)), \
g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); \
}
SIMD_BINOP_LIST(VISIT_SIMD_BINOP)
#undef VISIT_SIMD_BINOP
SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
#undef SIMD_VISIT_BINOP
#undef SIMD_BINOP_LIST
void InstructionSelector::VisitI32x4Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4ReplaceLane(Node* node) { UNIMPLEMENTED(); }
#undef SIMD_TYPES
void InstructionSelector::VisitI32x4Shl(Node* node) { UNIMPLEMENTED(); }
......@@ -2590,10 +2615,6 @@ void InstructionSelector::VisitI32x4GtU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI32x4GeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ReplaceLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8Shl(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); }
......@@ -2640,10 +2661,6 @@ void InstructionSelector::VisitI16x8GeU(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16ReplaceLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
UNIMPLEMENTED();
}
......@@ -2698,10 +2715,6 @@ void InstructionSelector::VisitF32x4Lt(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Le(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Splat(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4ReplaceLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::EmitPrepareResults(
ZoneVector<PushParameter>* results, const CallDescriptor* call_descriptor,
Node* node) {
......@@ -2872,6 +2885,8 @@ void InstructionSelector::VisitF64x2Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF64x2ExtractLane(Node* node) { UNIMPLEMENTED(); }
// static
MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() {
......
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