[wasm-simd][arm64] Merge load splat opcodes

Load splat implementation is almost the same, except for the vector
format used for the output register. We encode this information in
MiscField (the size of each lane), and with some helper functions we can
easily reuse a single opcode for 4 load splats.

Bug: v8:10930
Change-Id: Ieed4dc7358821a0d1d7bab4add7a59d808c5aad8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2422354
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70098}

src/codegen/arm64/register-arm64.cc

@@ -136,6 +136,10 @@ VectorFormat ScalarFormatFromLaneSize(int laneSize) {
   }
 }
 
+VectorFormat VectorFormatFillQ(int laneSize) {
+  return VectorFormatFillQ(ScalarFormatFromLaneSize(laneSize));
+}
+
 VectorFormat ScalarFormatFromFormat(VectorFormat vform) {
   return ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
 }

src/codegen/arm64/register-arm64.h

@@ -281,6 +281,7 @@ VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
 VectorFormat ScalarFormatFromLaneSize(int lanesize);
 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
+VectorFormat VectorFormatFillQ(int laneSize);
 VectorFormat VectorFormatFillQ(VectorFormat vform);
 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
 V8_EXPORT_PRIVATE unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
@@ -345,6 +346,10 @@ class VRegister : public CPURegister {
     return VRegister::Create(code(), kDRegSizeInBits, 1);
   }
 
+  VRegister Format(VectorFormat f) const {
+    return VRegister::Create(code(), f);
+  }
+
   bool Is8B() const { return (Is64Bits() && (lane_count_ == 8)); }
   bool Is16B() const { return (Is128Bits() && (lane_count_ == 16)); }
   bool Is4H() const { return (Is64Bits() && (lane_count_ == 4)); }

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -2601,20 +2601,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Add(i.OutputRegister32(), i.OutputRegister32(), 1);
       break;
     }
-    case kArm64S8x16LoadSplat: {
-      __ ld1r(i.OutputSimd128Register().V16B(), i.MemoryOperand(0));
-      break;
-    }
-    case kArm64S16x8LoadSplat: {
-      __ ld1r(i.OutputSimd128Register().V8H(), i.MemoryOperand(0));
-      break;
-    }
-    case kArm64S32x4LoadSplat: {
-      __ ld1r(i.OutputSimd128Register().V4S(), i.MemoryOperand(0));
-      break;
-    }
-    case kArm64S64x2LoadSplat: {
-      __ ld1r(i.OutputSimd128Register().V2D(), i.MemoryOperand(0));
+    case kArm64LoadSplat: {
+      VectorFormat f = VectorFormatFillQ(MiscField::decode(opcode));
+      __ ld1r(i.OutputSimd128Register().Format(f), i.MemoryOperand(0));
       break;
     }
     case kArm64I16x8Load8x8S: {

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -380,10 +380,7 @@ namespace compiler {
   V(Arm64V32x4AllTrue)                      \
   V(Arm64V16x8AllTrue)                      \
   V(Arm64V8x16AllTrue)                      \
-  V(Arm64S8x16LoadSplat)                    \
-  V(Arm64S16x8LoadSplat)                    \
-  V(Arm64S32x4LoadSplat)                    \
-  V(Arm64S64x2LoadSplat)                    \
+  V(Arm64LoadSplat)                         \
   V(Arm64I16x8Load8x8S)                     \
   V(Arm64I16x8Load8x8U)                     \
   V(Arm64I32x4Load16x4S)                    \

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -370,10 +370,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64LdrDecompressTaggedPointer:
     case kArm64LdrDecompressAnyTagged:
     case kArm64Peek:
-    case kArm64S8x16LoadSplat:
-    case kArm64S16x8LoadSplat:
-    case kArm64S32x4LoadSplat:
-    case kArm64S64x2LoadSplat:
+    case kArm64LoadSplat:
     case kArm64I16x8Load8x8S:
     case kArm64I16x8Load8x8U:
     case kArm64I32x4Load16x4S:

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -607,19 +607,23 @@ void InstructionSelector::VisitLoadTransform(Node* node) {
   bool require_add = false;
   switch (params.transformation) {
     case LoadTransformation::kS8x16LoadSplat:
-      opcode = kArm64S8x16LoadSplat;
+      opcode = kArm64LoadSplat;
+      opcode |= MiscField::encode(8);
       require_add = true;
       break;
     case LoadTransformation::kS16x8LoadSplat:
-      opcode = kArm64S16x8LoadSplat;
+      opcode = kArm64LoadSplat;
+      opcode |= MiscField::encode(16);
       require_add = true;
       break;
     case LoadTransformation::kS32x4LoadSplat:
-      opcode = kArm64S32x4LoadSplat;
+      opcode = kArm64LoadSplat;
+      opcode |= MiscField::encode(32);
       require_add = true;
       break;
     case LoadTransformation::kS64x2LoadSplat:
-      opcode = kArm64S64x2LoadSplat;
+      opcode = kArm64LoadSplat;
+      opcode |= MiscField::encode(64);
       require_add = true;
       break;
     case LoadTransformation::kI16x8Load8x8S: