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Commit aada6a3a authored by sreten.kovacevic's avatar sreten.kovacevic Committed by Commit Bot
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MIPS[64]: Fixed issue with atomics test 

Fixed issue with UseScratchRegisterScope that made test fail on r1
and wrong register usage on all arch variants.

Bug: 
Change-Id: Id89ff84046d012dd0767b9031b2719f9a95a08b8
Reviewed-on: https://chromium-review.googlesource.com/667139Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#48030}
parent c886dfd3
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Showing with 29 additions and 25 deletions
src/compiler/mips/code-generator-mips.cc
View file @ aada6a3a
......@@ -575,16 +575,17 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
__ sync(); \
} while (0)
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER() \
do { \
Label exchange; \
__ sync(); \
__ bind(&exchange); \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
__ Sc(i.InputRegister(2), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&exchange, eq, i.InputRegister(2), Operand(zero_reg)); \
__ sync(); \
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER() \
do { \
Label exchange; \
__ sync(); \
__ bind(&exchange); \
__ addu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
__ mov(i.TempRegister(1), i.InputRegister(2)); \
__ Sc(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&exchange, eq, i.TempRegister(1), Operand(zero_reg)); \
__ sync(); \
} while (0)
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(sign_extend, size) \
......@@ -616,8 +617,9 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&exit, ne, i.InputRegister(2), \
Operand(i.OutputRegister(0))); \
__ Sc(i.InputRegister(3), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&compareExchange, eq, i.InputRegister(3), \
__ mov(i.TempRegister(2), i.InputRegister(3)); \
__ Sc(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&compareExchange, eq, i.TempRegister(2), \
Operand(zero_reg)); \
__ bind(&exit); \
__ sync(); \
......
src/compiler/mips64/code-generator-mips64.cc
View file @ aada6a3a
......@@ -612,16 +612,17 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
__ sync(); \
} while (0)
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER() \
do { \
Label exchange; \
__ sync(); \
__ bind(&exchange); \
__ daddu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
__ Sc(i.InputRegister(2), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&exchange, eq, i.InputRegister(2), Operand(zero_reg)); \
__ sync(); \
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER() \
do { \
Label exchange; \
__ sync(); \
__ bind(&exchange); \
__ daddu(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
__ mov(i.TempRegister(1), i.InputRegister(2)); \
__ Sc(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&exchange, eq, i.TempRegister(1), Operand(zero_reg)); \
__ sync(); \
} while (0)
#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(sign_extend, size) \
......@@ -654,8 +655,9 @@ FPUCondition FlagsConditionToConditionCmpFPU(bool& predicate,
__ Ll(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&exit, ne, i.InputRegister(2), \
Operand(i.OutputRegister(0))); \
__ Sc(i.InputRegister(3), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&compareExchange, eq, i.InputRegister(3), \
__ mov(i.TempRegister(2), i.InputRegister(3)); \
__ Sc(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \
__ BranchShort(&compareExchange, eq, i.TempRegister(2), \
Operand(zero_reg)); \
__ bind(&exit); \
__ sync(); \
......
src/mips/macro-assembler-mips.cc
View file @ aada6a3a
......@@ -979,7 +979,7 @@ void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) {
} else {
if (rt.is_reg()) {
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Register scratch = temps.hasAvailable() ? temps.Acquire() : t8;
subu(scratch, zero_reg, rt.rm());
sllv(scratch, rs, scratch);
srlv(rd, rs, rt.rm());
......
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