Revert "[x64][ia32] Set lower SSE flags when newer extensions are enabled"

This reverts commit b49638c5.

Reason for revert: Buggy for avx2 and --no-enabled-sse4-2 (but avx is available on bots), see review comments for details.

Original change's description:
> [x64][ia32] Set lower SSE flags when newer extensions are enabled
>
> If SSE4.2 is enabled, all the previous extensions should also be
> enabled. In particular, you cannot have --enable-sse4_1 and
> --no-enable-sse3.
>
> Bug: chromium:1195579
> Change-Id: Id3e10db24cee2aee14449a77c9e7cff82e97edff
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2808621
> Reviewed-by: Andreas Haas <ahaas@chromium.org>
> Reviewed-by: Clemens Backes <clemensb@chromium.org>
> Commit-Queue: Zhi An Ng <zhin@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#73840}

Tbr: ahaas@chromium.org,clemensb@chromium.org
Bug: chromium:1195579
Change-Id: Iabce159a82e8b71cbec8336091323f35e9aff16e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2818562Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Cr-Commit-Position: refs/heads/master@{#73885}

src/codegen/ia32/assembler-ia32.cc

@@ -138,9 +138,14 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Only use statically determined features for cross compile (snapshot).
   if (cross_compile) return;
 
-  // To deal with any combination of flags (e.g. --no-enable-sse4-1
-  // --enable-sse-4-2), we start checking from the "highest" supported
-  // extension, for each extension, enable if newer extension is supported.
+  if (cpu.has_sse42() && FLAG_enable_sse4_2) supported_ |= 1u << SSE4_2;
+  if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
+  if (cpu.has_ssse3() && FLAG_enable_ssse3) supported_ |= 1u << SSSE3;
+  if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
+  if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
+      OSHasAVXSupport()) {
+    supported_ |= 1u << AVX;
+  }
   if (cpu.has_avx2() && FLAG_enable_avx2 && IsSupported(AVX)) {
     supported_ |= 1u << AVX2;
   }
@@ -148,19 +153,6 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
       OSHasAVXSupport()) {
     supported_ |= 1u << FMA3;
   }
-  if ((cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
-       OSHasAVXSupport()) ||
-      IsSupported(AVX2) || IsSupported(FMA3)) {
-    supported_ |= 1u << AVX;
-  }
-  if ((cpu.has_sse42() && FLAG_enable_sse4_2) || IsSupported(AVX))
-    supported_ |= 1u << SSE4_2;
-  if ((cpu.has_sse41() && FLAG_enable_sse4_1) || IsSupported(SSE4_2))
-    supported_ |= 1u << SSE4_1;
-  if ((cpu.has_ssse3() && FLAG_enable_ssse3) || IsSupported(SSE4_1))
-    supported_ |= 1u << SSSE3;
-  if ((cpu.has_sse3() && FLAG_enable_sse3) || IsSupported(SSSE3))
-    supported_ |= 1u << SSE3;
   if (cpu.has_bmi1() && FLAG_enable_bmi1) supported_ |= 1u << BMI1;
   if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2;
   if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;

src/codegen/x64/assembler-x64.cc

@@ -87,9 +87,19 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Only use statically determined features for cross compile (snapshot).
   if (cross_compile) return;
 
-  // To deal with any combination of flags (e.g. --no-enable-sse4-1
-  // --enable-sse-4-2), we start checking from the "highest" supported
-  // extension, for each extension, enable if newer extension is supported.
+  if (cpu.has_sse42() && FLAG_enable_sse4_2) supported_ |= 1u << SSE4_2;
+  if (cpu.has_sse41() && FLAG_enable_sse4_1) {
+    supported_ |= 1u << SSE4_1;
+    supported_ |= 1u << SSSE3;
+  }
+  if (cpu.has_ssse3() && FLAG_enable_ssse3) supported_ |= 1u << SSSE3;
+  if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
+  // SAHF is not generally available in long mode.
+  if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF;
+  if (cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
+      OSHasAVXSupport()) {
+    supported_ |= 1u << AVX;
+  }
   if (cpu.has_avx2() && FLAG_enable_avx2 && IsSupported(AVX)) {
     supported_ |= 1u << AVX2;
   }
@@ -97,24 +107,6 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
       OSHasAVXSupport()) {
     supported_ |= 1u << FMA3;
   }
-  if ((cpu.has_avx() && FLAG_enable_avx && cpu.has_osxsave() &&
-       OSHasAVXSupport()) ||
-      IsSupported(AVX2) || IsSupported(FMA3)) {
-    supported_ |= 1u << AVX;
-  }
-  if ((cpu.has_sse42() && FLAG_enable_sse4_2) || IsSupported(AVX)) {
-    supported_ |= 1u << SSE4_2;
-  }
-  if ((cpu.has_sse41() && FLAG_enable_sse4_1) || IsSupported(SSE4_2)) {
-    supported_ |= 1u << SSE4_1;
-  }
-  if ((cpu.has_ssse3() && FLAG_enable_ssse3) || IsSupported(SSE4_1)) {
-    supported_ |= 1u << SSSE3;
-  }
-  if ((cpu.has_sse3() && FLAG_enable_sse3) || IsSupported(SSSE3))
-    supported_ |= 1u << SSE3;
-  // SAHF is not generally available in long mode.
-  if (cpu.has_sahf() && FLAG_enable_sahf) supported_ |= 1u << SAHF;
   if (cpu.has_bmi1() && FLAG_enable_bmi1) supported_ |= 1u << BMI1;
   if (cpu.has_bmi2() && FLAG_enable_bmi2) supported_ |= 1u << BMI2;
   if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT;