MIPS64: Fix code generator and simulator for DEXTM.

In code generator, DEXTM instruction will be emitted for intervals
position=[0,31] and size=[33,64]. In simulator, mask for DEXTM will be
calculated on correct way for size = 64. Disassembler has now possibility
to disassemble instructions DEXTM and DEXTU.

TEST=cctest/test-run-machops/Regression6122
BUG=

Review-Url: https://codereview.chromium.org/2769403002
Cr-Commit-Position: refs/heads/master@{#44137}

src/compiler/mips64/code-generator-mips64.cc

@@ -1221,7 +1221,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       if (size > 0 && size <= 32 && pos >= 0 && pos < 32) {
         __ Dext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1),
                 i.InputInt8(2));
-      } else if (size > 32 && size <= 64 && pos > 0 && pos < 32) {
+      } else if (size > 32 && size <= 64 && pos >= 0 && pos < 32) {
         __ Dextm(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1),
                  i.InputInt8(2));
       } else {

src/mips64/disasm-mips64.cc

@@ -1473,6 +1473,14 @@ void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
       Format(instr, "dext    'rt, 'rs, 'sa, 'ss1");
       break;
     }
+    case DEXTM: {
+      Format(instr, "dextm   'rt, 'rs, 'sa, 'ss1");
+      break;
+    }
+    case DEXTU: {
+      Format(instr, "dextu   'rt, 'rs, 'sa, 'ss1");
+      break;
+    }
     case BSHFL: {
       int sa = instr->SaFieldRaw() >> kSaShift;
       switch (sa) {

src/mips64/simulator-mips64.cc

@@ -4072,7 +4072,7 @@ void Simulator::DecodeTypeRegisterSPECIAL3() {
       // Interpret sa field as 5-bit lsb of extract.
       uint16_t lsb = sa();
       uint16_t size = msb + 1;
-      uint64_t mask = (1ULL << size) - 1;
+      uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
       alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
       SetResult(rt_reg(), alu_out);
       break;
@@ -4083,7 +4083,7 @@ void Simulator::DecodeTypeRegisterSPECIAL3() {
       // Interpret sa field as 5-bit lsb of extract.
       uint16_t lsb = sa();
       uint16_t size = msb + 33;
-      uint64_t mask = (1ULL << size) - 1;
+      uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
       alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
       SetResult(rt_reg(), alu_out);
       break;
@@ -4094,7 +4094,7 @@ void Simulator::DecodeTypeRegisterSPECIAL3() {
       // Interpret sa field as 5-bit lsb of extract.
       uint16_t lsb = sa() + 32;
       uint16_t size = msb + 1;
-      uint64_t mask = (1ULL << size) - 1;
+      uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
       alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
       SetResult(rt_reg(), alu_out);
       break;