Commit a59605ef authored by mtrofin's avatar mtrofin Committed by Commit bot

Validate that instruction selection maintains SSA form.

It benefits certain algorithms in register allocation to assume the input is
SSA - understanding that ResolvePhis in the regalloc pipeline lowers
phis, thus blurring the SSA invariant.

BUG=

Review URL: https://codereview.chromium.org/1760323002

Cr-Commit-Position: refs/heads/master@{#34509}
parent 35bce027
......@@ -82,6 +82,9 @@ void InstructionSelector::SelectInstructions() {
}
EndBlock(RpoNumber::FromInt(block->rpo_number()));
}
#if DEBUG
sequence()->ValidateSSA();
#endif
}
......
......@@ -620,7 +620,7 @@ InstructionBlocks* InstructionSequence::InstructionBlocksFor(
return blocks;
}
void InstructionSequence::Validate() {
void InstructionSequence::ValidateEdgeSplitForm() {
// Validate blocks are in edge-split form: no block with multiple successors
// has an edge to a block (== a successor) with more than one predecessors.
for (const InstructionBlock* block : instruction_blocks()) {
......@@ -635,6 +635,21 @@ void InstructionSequence::Validate() {
}
}
void InstructionSequence::ValidateSSA() {
// TODO(mtrofin): We could use a local zone here instead.
BitVector definitions(VirtualRegisterCount(), zone());
for (const Instruction* instruction : *this) {
for (size_t i = 0; i < instruction->OutputCount(); ++i) {
const InstructionOperand* output = instruction->OutputAt(i);
int vreg = (output->IsConstant())
? ConstantOperand::cast(output)->virtual_register()
: UnallocatedOperand::cast(output)->virtual_register();
CHECK(!definitions.Contains(vreg));
definitions.Add(vreg);
}
}
}
void InstructionSequence::ComputeAssemblyOrder(InstructionBlocks* blocks) {
int ao = 0;
for (InstructionBlock* const block : *blocks) {
......@@ -669,7 +684,7 @@ InstructionSequence::InstructionSequence(Isolate* isolate,
block_starts_.reserve(instruction_blocks_->size());
#if DEBUG
Validate();
ValidateEdgeSplitForm();
#endif
}
......
......@@ -1354,7 +1354,8 @@ class InstructionSequence final : public ZoneObject {
void PrintBlock(const RegisterConfiguration* config, int block_id) const;
void PrintBlock(int block_id) const;
void Validate();
void ValidateEdgeSplitForm();
void ValidateSSA();
private:
friend std::ostream& operator<<(std::ostream& os,
......
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