[riscv64] Fix name ambiguous

Change-Id: I30042811cec8fc2821b7a240c2f8b4e748f437e1
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3673913Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#80794}

src/codegen/riscv64/assembler-riscv64.cc

@@ -876,7 +876,7 @@ void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode,
 
 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, Register rd,
                            Register rs1, Register rs2, Register rs3,
-                           RoundingMode frm) {
+                           FPURoundingMode frm) {
   DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() &&
          rs2.is_valid() && rs3.is_valid() && is_uint3(frm));
   Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
@@ -887,7 +887,7 @@ void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, Register rd,
 
 void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd,
                            FPURegister rs1, FPURegister rs2, FPURegister rs3,
-                           RoundingMode frm) {
+                           FPURoundingMode frm) {
   DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() &&
          rs2.is_valid() && rs3.is_valid() && is_uint3(frm));
   Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
@@ -908,7 +908,7 @@ void Assembler::GenInstrRAtomic(uint8_t funct5, bool aq, bool rl,
 }
 
 void Assembler::GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd,
-                             Register rs1, Register rs2, RoundingMode frm) {
+                             Register rs1, Register rs2, FPURoundingMode frm) {
   DCHECK(rd.is_valid() && rs1.is_valid() && rs2.is_valid() && is_uint3(frm));
   Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) |
                 (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) |
@@ -1957,46 +1957,46 @@ void Assembler::fsw(FPURegister source, Register base, int16_t imm12) {
 }
 
 void Assembler::fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                        FPURegister rs3, RoundingMode frm) {
+                        FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b00, MADD, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                        FPURegister rs3, RoundingMode frm) {
+                        FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b00, MSUB, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                         FPURegister rs3, RoundingMode frm) {
+                         FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b00, NMSUB, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                         FPURegister rs3, RoundingMode frm) {
+                         FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b00, NMADD, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0000000, frm, rd, rs1, rs2);
 }
 
 void Assembler::fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0000100, frm, rd, rs1, rs2);
 }
 
 void Assembler::fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0001000, frm, rd, rs1, rs2);
 }
 
 void Assembler::fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0001100, frm, rd, rs1, rs2);
 }
 
-void Assembler::fsqrt_s(FPURegister rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fsqrt_s(FPURegister rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0101100, frm, rd, rs1, zero_reg);
 }
 
@@ -2020,11 +2020,11 @@ void Assembler::fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
   GenInstrALUFP_rr(0b0010100, 0b001, rd, rs1, rs2);
 }
 
-void Assembler::fcvt_w_s(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_w_s(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100000, frm, rd, rs1, zero_reg);
 }
 
-void Assembler::fcvt_wu_s(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_wu_s(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(1));
 }
 
@@ -2048,11 +2048,11 @@ void Assembler::fclass_s(Register rd, FPURegister rs1) {
   GenInstrALUFP_rr(0b1110000, 0b001, rd, rs1, zero_reg);
 }
 
-void Assembler::fcvt_s_w(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_s_w(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101000, frm, rd, rs1, zero_reg);
 }
 
-void Assembler::fcvt_s_wu(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_s_wu(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(1));
 }
 
@@ -2062,19 +2062,19 @@ void Assembler::fmv_w_x(FPURegister rd, Register rs1) {
 
 // RV64F Standard Extension (in addition to RV32F)
 
-void Assembler::fcvt_l_s(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_l_s(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(2));
 }
 
-void Assembler::fcvt_lu_s(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_lu_s(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(3));
 }
 
-void Assembler::fcvt_s_l(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_s_l(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(2));
 }
 
-void Assembler::fcvt_s_lu(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_s_lu(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(3));
 }
 
@@ -2089,46 +2089,46 @@ void Assembler::fsd(FPURegister source, Register base, int16_t imm12) {
 }
 
 void Assembler::fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                        FPURegister rs3, RoundingMode frm) {
+                        FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b01, MADD, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                        FPURegister rs3, RoundingMode frm) {
+                        FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b01, MSUB, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                         FPURegister rs3, RoundingMode frm) {
+                         FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b01, NMSUB, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                         FPURegister rs3, RoundingMode frm) {
+                         FPURegister rs3, FPURoundingMode frm) {
   GenInstrR4(0b01, NMADD, rd, rs1, rs2, rs3, frm);
 }
 
 void Assembler::fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0000001, frm, rd, rs1, rs2);
 }
 
 void Assembler::fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0000101, frm, rd, rs1, rs2);
 }
 
 void Assembler::fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0001001, frm, rd, rs1, rs2);
 }
 
 void Assembler::fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                       RoundingMode frm) {
+                       FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0001101, frm, rd, rs1, rs2);
 }
 
-void Assembler::fsqrt_d(FPURegister rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fsqrt_d(FPURegister rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0101101, frm, rd, rs1, zero_reg);
 }
 
@@ -2152,11 +2152,11 @@ void Assembler::fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2) {
   GenInstrALUFP_rr(0b0010101, 0b001, rd, rs1, rs2);
 }
 
-void Assembler::fcvt_s_d(FPURegister rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_s_d(FPURegister rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0100000, frm, rd, rs1, ToRegister(1));
 }
 
-void Assembler::fcvt_d_s(FPURegister rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_d_s(FPURegister rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b0100001, frm, rd, rs1, zero_reg);
 }
 
@@ -2176,29 +2176,29 @@ void Assembler::fclass_d(Register rd, FPURegister rs1) {
   GenInstrALUFP_rr(0b1110001, 0b001, rd, rs1, zero_reg);
 }
 
-void Assembler::fcvt_w_d(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_w_d(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100001, frm, rd, rs1, zero_reg);
 }
 
-void Assembler::fcvt_wu_d(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_wu_d(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(1));
 }
 
-void Assembler::fcvt_d_w(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_d_w(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101001, frm, rd, rs1, zero_reg);
 }
 
-void Assembler::fcvt_d_wu(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_d_wu(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(1));
 }
 
 // RV64D Standard Extension (in addition to RV32D)
 
-void Assembler::fcvt_l_d(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_l_d(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(2));
 }
 
-void Assembler::fcvt_lu_d(Register rd, FPURegister rs1, RoundingMode frm) {
+void Assembler::fcvt_lu_d(Register rd, FPURegister rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(3));
 }
 
@@ -2206,11 +2206,11 @@ void Assembler::fmv_x_d(Register rd, FPURegister rs1) {
   GenInstrALUFP_rr(0b1110001, 0b000, rd, rs1, zero_reg);
 }
 
-void Assembler::fcvt_d_l(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_d_l(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(2));
 }
 
-void Assembler::fcvt_d_lu(FPURegister rd, Register rs1, RoundingMode frm) {
+void Assembler::fcvt_d_lu(FPURegister rd, Register rs1, FPURoundingMode frm) {
   GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(3));
 }
 

src/codegen/riscv64/assembler-riscv64.h

@@ -532,86 +532,86 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   void flw(FPURegister rd, Register rs1, int16_t imm12);
   void fsw(FPURegister source, Register base, int16_t imm12);
   void fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-               FPURegister rs3, RoundingMode frm = RNE);
+               FPURegister rs3, FPURoundingMode frm = RNE);
   void fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-               FPURegister rs3, RoundingMode frm = RNE);
+               FPURegister rs3, FPURoundingMode frm = RNE);
   void fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                FPURegister rs3, RoundingMode frm = RNE);
+                FPURegister rs3, FPURoundingMode frm = RNE);
   void fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                FPURegister rs3, RoundingMode frm = RNE);
+                FPURegister rs3, FPURoundingMode frm = RNE);
   void fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
   void fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
   void fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
   void fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
-  void fsqrt_s(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
+  void fsqrt_s(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE);
   void fsgnj_s(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fsgnjn_s(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fsgnjx_s(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2);
-  void fcvt_w_s(Register rd, FPURegister rs1, RoundingMode frm = RNE);
-  void fcvt_wu_s(Register rd, FPURegister rs1, RoundingMode frm = RNE);
+  void fcvt_w_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
+  void fcvt_wu_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
   void fmv_x_w(Register rd, FPURegister rs1);
   void feq_s(Register rd, FPURegister rs1, FPURegister rs2);
   void flt_s(Register rd, FPURegister rs1, FPURegister rs2);
   void fle_s(Register rd, FPURegister rs1, FPURegister rs2);
   void fclass_s(Register rd, FPURegister rs1);
-  void fcvt_s_w(FPURegister rd, Register rs1, RoundingMode frm = RNE);
-  void fcvt_s_wu(FPURegister rd, Register rs1, RoundingMode frm = RNE);
+  void fcvt_s_w(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
+  void fcvt_s_wu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
   void fmv_w_x(FPURegister rd, Register rs1);
 
   // RV64F Standard Extension (in addition to RV32F)
-  void fcvt_l_s(Register rd, FPURegister rs1, RoundingMode frm = RNE);
-  void fcvt_lu_s(Register rd, FPURegister rs1, RoundingMode frm = RNE);
-  void fcvt_s_l(FPURegister rd, Register rs1, RoundingMode frm = RNE);
-  void fcvt_s_lu(FPURegister rd, Register rs1, RoundingMode frm = RNE);
+  void fcvt_l_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
+  void fcvt_lu_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
+  void fcvt_s_l(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
+  void fcvt_s_lu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
 
   // RV32D Standard Extension
   void fld(FPURegister rd, Register rs1, int16_t imm12);
   void fsd(FPURegister source, Register base, int16_t imm12);
   void fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-               FPURegister rs3, RoundingMode frm = RNE);
+               FPURegister rs3, FPURoundingMode frm = RNE);
   void fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-               FPURegister rs3, RoundingMode frm = RNE);
+               FPURegister rs3, FPURoundingMode frm = RNE);
   void fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                FPURegister rs3, RoundingMode frm = RNE);
+                FPURegister rs3, FPURoundingMode frm = RNE);
   void fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-                FPURegister rs3, RoundingMode frm = RNE);
+                FPURegister rs3, FPURoundingMode frm = RNE);
   void fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
   void fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
   void fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
   void fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2,
-              RoundingMode frm = RNE);
-  void fsqrt_d(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE);
+              FPURoundingMode frm = RNE);
+  void fsqrt_d(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE);
   void fsgnj_d(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fsgnjn_d(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fsgnjx_d(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2);
   void fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2);
-  void fcvt_s_d(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE);
-  void fcvt_d_s(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE);
+  void fcvt_s_d(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE);
+  void fcvt_d_s(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE);
   void feq_d(Register rd, FPURegister rs1, FPURegister rs2);
   void flt_d(Register rd, FPURegister rs1, FPURegister rs2);
   void fle_d(Register rd, FPURegister rs1, FPURegister rs2);
   void fclass_d(Register rd, FPURegister rs1);
-  void fcvt_w_d(Register rd, FPURegister rs1, RoundingMode frm = RNE);
-  void fcvt_wu_d(Register rd, FPURegister rs1, RoundingMode frm = RNE);
-  void fcvt_d_w(FPURegister rd, Register rs1, RoundingMode frm = RNE);
-  void fcvt_d_wu(FPURegister rd, Register rs1, RoundingMode frm = RNE);
+  void fcvt_w_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
+  void fcvt_wu_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
+  void fcvt_d_w(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
+  void fcvt_d_wu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
 
   // RV64D Standard Extension (in addition to RV32D)
-  void fcvt_l_d(Register rd, FPURegister rs1, RoundingMode frm = RNE);
-  void fcvt_lu_d(Register rd, FPURegister rs1, RoundingMode frm = RNE);
+  void fcvt_l_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
+  void fcvt_lu_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE);
   void fmv_x_d(Register rd, FPURegister rs1);
-  void fcvt_d_l(FPURegister rd, Register rs1, RoundingMode frm = RNE);
-  void fcvt_d_lu(FPURegister rd, Register rs1, RoundingMode frm = RNE);
+  void fcvt_d_l(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
+  void fcvt_d_lu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE);
   void fmv_d_x(FPURegister rd, Register rs1);
 
   // RV64C Standard Extension
@@ -1350,7 +1350,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
       set(rd, VSew(sew), Vlmul(lmul));
     }
 
-    void set(RoundingMode mode) {
+    void set(FPURoundingMode mode) {
       if (mode_ != mode) {
         assm_->addi(kScratchReg, zero_reg, mode << kFcsrFrmShift);
         assm_->fscsr(kScratchReg);
@@ -1379,7 +1379,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
     Vlmul lmul_ = m1;
     int32_t vl = 0;
     Assembler* assm_;
-    RoundingMode mode_ = RNE;
+    FPURoundingMode mode_ = RNE;
   };
 
   VectorUnit VU;
@@ -1561,14 +1561,14 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
   void GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, Register rd,
                  FPURegister rs1, FPURegister rs2);
   void GenInstrR4(uint8_t funct2, Opcode opcode, Register rd, Register rs1,
-                  Register rs2, Register rs3, RoundingMode frm);
+                  Register rs2, Register rs3, FPURoundingMode frm);
   void GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd,
                   FPURegister rs1, FPURegister rs2, FPURegister rs3,
-                  RoundingMode frm);
+                  FPURoundingMode frm);
   void GenInstrRAtomic(uint8_t funct5, bool aq, bool rl, uint8_t funct3,
                        Register rd, Register rs1, Register rs2);
   void GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd, Register rs1,
-                    Register rs2, RoundingMode frm);
+                    Register rs2, FPURoundingMode frm);
   void GenInstrI(uint8_t funct3, Opcode opcode, Register rd, Register rs1,
                  int16_t imm12);
   void GenInstrI(uint8_t funct3, Opcode opcode, FPURegister rd, Register rs1,

src/codegen/riscv64/constants-riscv64.h

@@ -1219,7 +1219,7 @@ enum FFlagsMask {
   kInexact = 0b1                // NX:  Inexact
 };
 
-enum RoundingMode {
+enum FPURoundingMode {
   RNE = 0b000,  // Round to Nearest, ties to Even
   RTZ = 0b001,  // Round towards Zero
   RDN = 0b010,  // Round Down (towards -infinity)

src/codegen/riscv64/macro-assembler-riscv64.cc

@@ -1986,7 +1986,7 @@ void TurboAssembler::Floor_w_d(Register rd, FPURegister fs, Register result) {
 // handling is needed by NaN, +/-Infinity, +/-0
 template <typename F>
 void TurboAssembler::RoundHelper(FPURegister dst, FPURegister src,
-                                 FPURegister fpu_scratch, RoundingMode frm) {
+                                 FPURegister fpu_scratch, FPURoundingMode frm) {
   BlockTrampolinePoolScope block_trampoline_pool(this);
   UseScratchRegisterScope temps(this);
   Register scratch2 = temps.Acquire();
@@ -2106,7 +2106,7 @@ void TurboAssembler::RoundHelper(FPURegister dst, FPURegister src,
 // handling is needed by NaN, +/-Infinity, +/-0
 template <typename F>
 void TurboAssembler::RoundHelper(VRegister dst, VRegister src, Register scratch,
-                                 VRegister v_scratch, RoundingMode frm) {
+                                 VRegister v_scratch, FPURoundingMode frm) {
   VU.set(scratch, std::is_same<F, float>::value ? E32 : E64, m1);
   // if src is NaN/+-Infinity/+-Zero or if the exponent is larger than # of bits
   // in mantissa, the result is the same as src, so move src to dest  (to avoid

src/codegen/riscv64/macro-assembler-riscv64.h

@@ -1022,11 +1022,11 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
 
   template <typename F_TYPE>
   void RoundHelper(FPURegister dst, FPURegister src, FPURegister fpu_scratch,
-                   RoundingMode mode);
+                   FPURoundingMode mode);
 
   template <typename F>
   void RoundHelper(VRegister dst, VRegister src, Register scratch,
-                   VRegister v_scratch, RoundingMode frm);
+                   VRegister v_scratch, FPURoundingMode frm);
 
   template <typename TruncFunc>
   void RoundFloatingPointToInteger(Register rd, FPURegister fs, Register result,

src/compiler/backend/riscv64/code-generator-riscv64.cc

@@ -2294,7 +2294,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vmfeq_vv(v0, i.InputSimd128Register(0), i.InputSimd128Register(0));
       __ vmv_vv(kSimd128ScratchReg3, i.InputSimd128Register(0));
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vfncvt_x_f_w(kSimd128ScratchReg, kSimd128ScratchReg3, MaskType::Mask);
       __ vmv_vv(i.OutputSimd128Register(), kSimd128ScratchReg);
       break;
@@ -2305,7 +2305,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vmfeq_vv(v0, i.InputSimd128Register(0), i.InputSimd128Register(0));
       __ vmv_vv(kSimd128ScratchReg3, i.InputSimd128Register(0));
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vfncvt_xu_f_w(kSimd128ScratchReg, kSimd128ScratchReg3, MaskType::Mask);
       __ vmv_vv(i.OutputSimd128Register(), kSimd128ScratchReg);
       break;
@@ -2936,7 +2936,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
     case kRiscvF64x2Mul: {
       __ VU.set(kScratchReg, E64, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vfmul_vv(i.OutputSimd128Register(), i.InputSimd128Register(0),
                   i.InputSimd128Register(1));
       break;
@@ -3067,26 +3067,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
     case kRiscvF32x4UConvertI32x4: {
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vfcvt_f_xu_v(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
     case kRiscvF32x4SConvertI32x4: {
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vfcvt_f_x_v(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
     case kRiscvF32x4Div: {
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vfdiv_vv(i.OutputSimd128Register(), i.InputSimd128Register(0),
                   i.InputSimd128Register(1));
       break;
     }
     case kRiscvF32x4Mul: {
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vfmul_vv(i.OutputSimd128Register(), i.InputSimd128Register(1),
                   i.InputSimd128Register(0));
       break;
@@ -3231,7 +3231,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
     case kRiscvI32x4SConvertF32x4: {
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vmfeq_vv(v0, i.InputSimd128Register(0), i.InputSimd128Register(0));
       if (i.OutputSimd128Register() != i.InputSimd128Register(0)) {
         __ vmv_vx(i.OutputSimd128Register(), zero_reg);
@@ -3246,7 +3246,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
     case kRiscvI32x4UConvertF32x4: {
       __ VU.set(kScratchReg, E32, m1);
-      __ VU.set(RoundingMode::RTZ);
+      __ VU.set(FPURoundingMode::RTZ);
       __ vmfeq_vv(v0, i.InputSimd128Register(0), i.InputSimd128Register(0));
       if (i.OutputSimd128Register() != i.InputSimd128Register(0)) {
         __ vmv_vx(i.OutputSimd128Register(), zero_reg);
@@ -3303,7 +3303,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vmv_vv(v26, i.InputSimd128Register(0));
       __ vmv_vv(v27, i.InputSimd128Register(1));
       __ VU.set(kScratchReg, E8, m1);
-      __ VU.set(RoundingMode::RNE);
+      __ VU.set(FPURoundingMode::RNE);
       __ vnclip_vi(i.OutputSimd128Register(), v26, 0);
       break;
     }
@@ -3314,7 +3314,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ VU.set(kScratchReg, E16, m2);
       __ vmax_vx(v26, v26, zero_reg);
       __ VU.set(kScratchReg, E8, m1);
-      __ VU.set(RoundingMode::RNE);
+      __ VU.set(FPURoundingMode::RNE);
       __ vnclipu_vi(i.OutputSimd128Register(), v26, 0);
       break;
     }
@@ -3323,7 +3323,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vmv_vv(v26, i.InputSimd128Register(0));
       __ vmv_vv(v27, i.InputSimd128Register(1));
       __ VU.set(kScratchReg, E16, m1);
-      __ VU.set(RoundingMode::RNE);
+      __ VU.set(FPURoundingMode::RNE);
       __ vnclip_vi(i.OutputSimd128Register(), v26, 0);
       break;
     }
@@ -3334,7 +3334,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ VU.set(kScratchReg, E32, m2);
       __ vmax_vx(v26, v26, zero_reg);
       __ VU.set(kScratchReg, E16, m1);
-      __ VU.set(RoundingMode::RNE);
+      __ VU.set(FPURoundingMode::RNE);
       __ vnclipu_vi(i.OutputSimd128Register(), v26, 0);
       break;
     }

src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h

@@ -2387,7 +2387,7 @@ void LiftoffAssembler::emit_i32x4_trunc_sat_f64x2_s_zero(LiftoffRegister dst,
   vmfeq_vv(v0, src.fp().toV(), src.fp().toV());
   vmv_vv(kSimd128ScratchReg3, src.fp().toV());
   VU.set(kScratchReg, E32, m1);
-  VU.set(RoundingMode::RTZ);
+  VU.set(FPURoundingMode::RTZ);
   vfncvt_x_f_w(kSimd128ScratchReg, kSimd128ScratchReg3, MaskType::Mask);
   vmv_vv(dst.fp().toV(), kSimd128ScratchReg);
 }
@@ -2399,7 +2399,7 @@ void LiftoffAssembler::emit_i32x4_trunc_sat_f64x2_u_zero(LiftoffRegister dst,
   vmfeq_vv(v0, src.fp().toV(), src.fp().toV());
   vmv_vv(kSimd128ScratchReg3, src.fp().toV());
   VU.set(kScratchReg, E32, m1);
-  VU.set(RoundingMode::RTZ);
+  VU.set(FPURoundingMode::RTZ);
   vfncvt_xu_f_w(kSimd128ScratchReg, kSimd128ScratchReg3, MaskType::Mask);
   vmv_vv(dst.fp().toV(), kSimd128ScratchReg);
 }
@@ -3072,7 +3072,7 @@ void LiftoffAssembler::emit_f32x4_sub(LiftoffRegister dst, LiftoffRegister lhs,
 void LiftoffAssembler::emit_f32x4_mul(LiftoffRegister dst, LiftoffRegister lhs,
                                       LiftoffRegister rhs) {
   VU.set(kScratchReg, E32, m1);
-  VU.set(RoundingMode::RTZ);
+  VU.set(FPURoundingMode::RTZ);
   vfmul_vv(dst.fp().toV(), lhs.fp().toV(), rhs.fp().toV());
 }
 
@@ -3263,7 +3263,7 @@ void LiftoffAssembler::emit_f64x2_pmax(LiftoffRegister dst, LiftoffRegister lhs,
 void LiftoffAssembler::emit_i32x4_sconvert_f32x4(LiftoffRegister dst,
                                                  LiftoffRegister src) {
   VU.set(kScratchReg, E32, m1);
-  VU.set(RoundingMode::RTZ);
+  VU.set(FPURoundingMode::RTZ);
   vmfeq_vv(v0, src.fp().toV(), src.fp().toV());
   vmv_vx(dst.fp().toV(), zero_reg);
   vfcvt_x_f_v(dst.fp().toV(), src.fp().toV(), Mask);
@@ -3272,7 +3272,7 @@ void LiftoffAssembler::emit_i32x4_sconvert_f32x4(LiftoffRegister dst,
 void LiftoffAssembler::emit_i32x4_uconvert_f32x4(LiftoffRegister dst,
                                                  LiftoffRegister src) {
   VU.set(kScratchReg, E32, m1);
-  VU.set(RoundingMode::RTZ);
+  VU.set(FPURoundingMode::RTZ);
   vmfeq_vv(v0, src.fp().toV(), src.fp().toV());
   vmv_vx(dst.fp().toV(), zero_reg);
   vfcvt_xu_f_v(dst.fp().toV(), src.fp().toV(), Mask);
@@ -3281,14 +3281,14 @@ void LiftoffAssembler::emit_i32x4_uconvert_f32x4(LiftoffRegister dst,
 void LiftoffAssembler::emit_f32x4_sconvert_i32x4(LiftoffRegister dst,
                                                  LiftoffRegister src) {
   VU.set(kScratchReg, E32, m1);
-  VU.set(RoundingMode::RTZ);
+  VU.set(FPURoundingMode::RTZ);
   vfcvt_f_x_v(dst.fp().toV(), src.fp().toV());
 }
 
 void LiftoffAssembler::emit_f32x4_uconvert_i32x4(LiftoffRegister dst,
                                                  LiftoffRegister src) {
   VU.set(kScratchReg, E32, m1);
-  VU.set(RoundingMode::RTZ);
+  VU.set(FPURoundingMode::RTZ);
   vfcvt_f_xu_v(dst.fp().toV(), src.fp().toV());
 }
 
@@ -3299,7 +3299,7 @@ void LiftoffAssembler::emit_i8x16_sconvert_i16x8(LiftoffRegister dst,
   vmv_vv(v26, lhs.fp().toV());
   vmv_vv(v27, lhs.fp().toV());
   VU.set(kScratchReg, E8, m1);
-  VU.set(RoundingMode::RNE);
+  VU.set(FPURoundingMode::RNE);
   vnclip_vi(dst.fp().toV(), v26, 0);
 }
 
@@ -3312,7 +3312,7 @@ void LiftoffAssembler::emit_i8x16_uconvert_i16x8(LiftoffRegister dst,
   VU.set(kScratchReg, E16, m2);
   vmax_vx(v26, v26, zero_reg);
   VU.set(kScratchReg, E8, m1);
-  VU.set(RoundingMode::RNE);
+  VU.set(FPURoundingMode::RNE);
   vnclipu_vi(dst.fp().toV(), v26, 0);
 }
 
@@ -3323,7 +3323,7 @@ void LiftoffAssembler::emit_i16x8_sconvert_i32x4(LiftoffRegister dst,
   vmv_vv(v26, lhs.fp().toV());
   vmv_vv(v27, lhs.fp().toV());
   VU.set(kScratchReg, E16, m1);
-  VU.set(RoundingMode::RNE);
+  VU.set(FPURoundingMode::RNE);
   vnclip_vi(dst.fp().toV(), v26, 0);
 }
 
@@ -3336,7 +3336,7 @@ void LiftoffAssembler::emit_i16x8_uconvert_i32x4(LiftoffRegister dst,
   VU.set(kScratchReg, E32, m2);
   vmax_vx(v26, v26, zero_reg);
   VU.set(kScratchReg, E16, m1);
-  VU.set(RoundingMode::RNE);
+  VU.set(FPURoundingMode::RNE);
   vnclipu_vi(dst.fp().toV(), v26, 0);
 }
 

test/cctest/test-assembler-riscv64.cc

@@ -2621,7 +2621,7 @@ static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift) {
 #define UTEST_RVV_VNCLIP_E32M2_E16M1(instr_name, sign)                       \
   TEST(RISCV_UTEST_##instr_name##_E32M2_E16M1) {                             \
     if (!CpuFeatures::IsSupported(RISCV_SIMD)) return;                       \
-    constexpr RoundingMode vxrm = RNE;                                       \
+    constexpr FPURoundingMode vxrm = RNE;                                    \
     CcTest::InitializeVM();                                                  \
     Isolate* isolate = CcTest::i_isolate();                                  \
     HandleScope scope(isolate);                                              \