[riscv] Fix asm atomic op test case failed

Change-Id: I406d211bdac02501b1bfefdf6ebb63b97bb02e44
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3815774Reviewed-by: Nico Hartmann <nicohartmann@chromium.org>
Commit-Queue: Yahan Lu <yahan@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#82279}

src/builtins/builtins-sharedarraybuffer-gen.cc

@@ -251,7 +251,7 @@ TF_BUILTIN(AtomicsLoad, SharedArrayBufferBuiltinsAssembler) {
   BIND(&u32);
   Return(ChangeUint32ToTagged(AtomicLoad<Uint32T>(
       AtomicMemoryOrder::kSeqCst, backing_store, WordShl(index_word, 2))));
-#if (V8_TARGET_ARCH_MIPS && !_MIPS_ARCH_MIPS32R6) || V8_TARGET_ARCH_RISCV32
+#if (V8_TARGET_ARCH_MIPS && !_MIPS_ARCH_MIPS32R6)
   BIND(&i64);
   Goto(&u64);
 
@@ -268,8 +268,7 @@ TF_BUILTIN(AtomicsLoad, SharedArrayBufferBuiltinsAssembler) {
   BIND(&u64);
   Return(BigIntFromUnsigned64(AtomicLoad64<AtomicUint64>(
       AtomicMemoryOrder::kSeqCst, backing_store, WordShl(index_word, 3))));
-#endif  //(V8_TARGET_ARCH_MIPS && !_MIPS_ARCH_MIPS32R6) ||
-        // V8_TARGET_ARCH_RISCV32
+#endif  //(V8_TARGET_ARCH_MIPS && !_MIPS_ARCH_MIPS32R6)
 
   // This shouldn't happen, we've already validated the type.
   BIND(&other);

src/compiler/backend/riscv/code-generator-riscv.cc

@@ -1981,7 +1981,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ PushCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);
       __ PrepareCallCFunction(5, 0, kScratchReg);
       __ add(a0, i.InputRegister(0), i.InputRegister(1));
-      __ Sw(i.InputRegister(5), MemOperand(sp, 16));
       __ CallCFunction(
           ExternalReference::atomic_pair_compare_exchange_function(), 5, 0);
       __ PopCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);
@@ -2162,7 +2161,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     break;                                                                 \
   case kAtomic##op##Word32:                                                \
     __ AddWord(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \
-    __ amoinst32(true, true, i.TempRegister(1), i.TempRegister(0),         \
+    __ amoinst32(true, true, i.OutputRegister(0), i.TempRegister(0),       \
                  i.InputRegister(2));                                      \
     break;
       ATOMIC_BINOP_CASE(Add, Add32, Add64, amoadd_w)  // todo: delete 64

src/compiler/backend/riscv/instruction-selector-riscv32.cc

@@ -1278,7 +1278,7 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   InstructionOperand inputs[] = {
       g.UseRegister(node->InputAt(0)),  g.UseRegister(node->InputAt(1)),
       g.UseFixed(node->InputAt(2), a1), g.UseFixed(node->InputAt(3), a2),
-      g.UseFixed(node->InputAt(4), a3), g.UseUniqueRegister(node->InputAt(5))};
+      g.UseFixed(node->InputAt(4), a3), g.UseFixed(node->InputAt(5), a4)};
 
   InstructionCode code = kRiscvWord32AtomicPairCompareExchange |
                          AddressingModeField::encode(kMode_MRI);

src/execution/riscv/simulator-riscv.cc

@@ -1845,6 +1845,39 @@ void RiscvDebugger::Debug() {
           PrintF("\n");
           cur++;
         }
+      } else if (strcmp(cmd, "memhex") == 0) {
+        sreg_t* cur = nullptr;
+        sreg_t* end = nullptr;
+        int next_arg = 1;
+        if (argc < 2) {
+          PrintF("Need to specify <address> to memhex command\n");
+          continue;
+        }
+        sreg_t value;
+        if (!GetValue(arg1, &value)) {
+          PrintF("%s unrecognized\n", arg1);
+          continue;
+        }
+        cur = reinterpret_cast<sreg_t*>(value);
+        next_arg++;
+
+        sreg_t words;
+        if (argc == next_arg) {
+          words = 10;
+        } else {
+          if (!GetValue(argv[next_arg], &words)) {
+            words = 10;
+          }
+        }
+        end = cur + words;
+
+        while (cur < end) {
+          PrintF("  0x%012" PRIxPTR " :  0x%016" REGIx_FORMAT
+                 "  %14" REGId_FORMAT " ",
+                 reinterpret_cast<intptr_t>(cur), *cur, *cur);
+          PrintF("\n");
+          cur++;
+        }
       } else if ((strcmp(cmd, "watch") == 0)) {
         if (argc < 2) {
           PrintF("Need to specify <address> to mem command\n");

src/runtime/runtime-atomics.cc

@@ -22,7 +22,7 @@ namespace internal {
 // Other platforms have CSA support, see builtins-sharedarraybuffer-gen.h.
 #if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_PPC64 || \
     V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X ||    \
-    V8_TARGET_ARCH_LOONG64 || V8_TARGET_ARCH_RISCV32 || V8_TARGET_ARCH_RISCV64
+    V8_TARGET_ARCH_LOONG64
 
 namespace {
 

src/wasm/baseline/riscv/liftoff-assembler-riscv32.h

@@ -772,15 +772,16 @@ void LiftoffAssembler::AtomicCompareExchange(
     Register dst_addr, Register offset_reg, uintptr_t offset_imm,
     LiftoffRegister expected, LiftoffRegister new_value, LiftoffRegister result,
     StoreType type) {
+  ASM_CODE_COMMENT(this);
   LiftoffRegList pinned{dst_addr, offset_reg, expected, new_value, result};
 
   if (type.value() == StoreType::kI64Store) {
     Register actual_addr = liftoff::CalculateActualAddress(
         this, dst_addr, offset_reg, offset_imm, kScratchReg);
+    Mv(a0, actual_addr);
     FrameScope scope(this, StackFrame::MANUAL);
     PushCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);
     PrepareCallCFunction(5, 0, kScratchReg);
-    Mv(a0, actual_addr);
     CallCFunction(ExternalReference::atomic_pair_compare_exchange_function(), 5,
                   0);
     PopCallerSaved(SaveFPRegsMode::kIgnore, a0, a1);

test/mjsunit/mjsunit.status

@@ -485,12 +485,12 @@
 
 ##############################################################################
 # 32-bit platforms
-['arch in (ia32, arm, mips, mipsel)', {
+['arch in (ia32, arm, mips, mipsel, riscv32)', {
   # Needs >2GB of available contiguous memory.
   'wasm/grow-huge-memory': [SKIP],
   'wasm/huge-memory': [SKIP],
   'wasm/huge-typedarray': [SKIP],
-}],  # 'arch in (ia32, arm, mips, mipsel)'
+}],  # 'arch in (ia32, arm, mips, mipsel, riscv32)'
 
 ##############################################################################
 ['arch == arm64', {
@@ -923,28 +923,10 @@
 }],  # 'arch == riscv64 or arch == riscv32'
 
 [ 'arch == riscv32' , {
-
-'wasm/compare-exchange64-stress':[SKIP],
-'asm/atomics-and':[SKIP],
-'asm/atomics-add':[SKIP],
-'asm/atomics-sub':[SKIP],
-'asm/atomics-or':[SKIP],
-'asm/atomics-xor':[SKIP],
-'harmony/atomics':[SKIP],
-'typedarray-growablesharedarraybuffer-atomics':[SKIP],
-'typedarray-resizablearraybuffer-atomics':[SKIP],
-
-
-'regress/wasm/regress-1079449':[SKIP],
-'wasm/grow-huge-memory':[SKIP],
-'wasm/huge-typedarray':[SKIP],
-'wasm/huge-memory':[SKIP],
 'wasm/generic-wrapper':[SKIP],
 'wasm/many-parameters':[SKIP],
-'wasm/atomics':['variant == stress', SKIP],
+'wasm/compare-exchange64-stress':[SKIP],
 'wasm/externref-globals-liftoff':['variant == stress_incremental_marking', SKIP],
-'regress/wasm/regress-1296876':['variant == stress', SKIP],
-'wasm/shared-memory':['variant == stress', SKIP],
 'wasm/stringrefs-js':['variant == stress_incremental_marking', SKIP],
 }], # 'arch == riscv32'