[mips64] Prevent input registers' value from changing in some 32-bit

operations.

Some 32-bit operations like kMips64And32, kMips64Or32 and kMips64Shr
overwrite the input registers' value by truncates the 64-bit value to
32 bits and sign-extends it,which may conflicts with later operatons
that need the input register's 64-bit value.

Change-Id: I29a5116999f7e851f38bdbcc5b066141a0617589
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1928503Reviewed-by: Tobias Tebbi <tebbi@chromium.org>
Commit-Queue: Tobias Tebbi <tebbi@chromium.org>
Auto-Submit: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#65426}

src/compiler/backend/mips64/code-generator-mips64.cc

@@ -1095,12 +1095,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kMips64And32:
       if (instr->InputAt(1)->IsRegister()) {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ sll(i.InputRegister(1), i.InputRegister(1), 0x0);
         __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       } else {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
         __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       }
       break;
     case kMips64Or:
@@ -1108,12 +1107,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kMips64Or32:
       if (instr->InputAt(1)->IsRegister()) {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ sll(i.InputRegister(1), i.InputRegister(1), 0x0);
         __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       } else {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
         __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       }
       break;
     case kMips64Nor:
@@ -1126,13 +1124,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kMips64Nor32:
       if (instr->InputAt(1)->IsRegister()) {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ sll(i.InputRegister(1), i.InputRegister(1), 0x0);
         __ Nor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       } else {
         DCHECK_EQ(0, i.InputOperand(1).immediate());
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
         __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg);
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       }
       break;
     case kMips64Xor:
@@ -1140,12 +1137,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kMips64Xor32:
       if (instr->InputAt(1)->IsRegister()) {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ sll(i.InputRegister(1), i.InputRegister(1), 0x0);
         __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       } else {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
         __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
+        __ sll(i.OutputRegister(), i.OutputRegister(), 0x0);
       }
       break;
     case kMips64Clz:
@@ -1185,23 +1181,23 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     case kMips64Shr:
       if (instr->InputAt(1)->IsRegister()) {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
+        __ sll(i.OutputRegister(), i.InputRegister(0), 0x0);
+        __ srlv(i.OutputRegister(), i.OutputRegister(), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ srl(i.OutputRegister(), i.InputRegister(0),
+        __ sll(i.OutputRegister(), i.InputRegister(0), 0x0);
+        __ srl(i.OutputRegister(), i.OutputRegister(),
                static_cast<uint16_t>(imm));
       }
       break;
     case kMips64Sar:
       if (instr->InputAt(1)->IsRegister()) {
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
+        __ sll(i.OutputRegister(), i.InputRegister(0), 0x0);
+        __ srav(i.OutputRegister(), i.OutputRegister(), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
-        __ sll(i.InputRegister(0), i.InputRegister(0), 0x0);
-        __ sra(i.OutputRegister(), i.InputRegister(0),
+        __ sll(i.OutputRegister(), i.InputRegister(0), 0x0);
+        __ sra(i.OutputRegister(), i.OutputRegister(),
                static_cast<uint16_t>(imm));
       }
       break;