[mipsr6] Implement functions for FPU conditional move

Since movf and movt instructions were removed in r6, sel_s and
sel_d instructions need to be used instead with some preparations.

Change-Id: Ia6a2fda7d3d79ada1ae1ec4649793efd2466f79b
Reviewed-on: https://chromium-review.googlesource.com/1016910Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Commit-Queue: Sreten Kovacevic <sreten.kovacevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#52683}

src/mips/macro-assembler-mips.cc

@@ -2406,6 +2406,24 @@ void TurboAssembler::LoadZeroIfConditionZero(Register dest,
   }
 }
 
+void TurboAssembler::LoadZeroIfFPUCondition(Register dest) {
+  if (IsMipsArchVariant(kMips32r6)) {
+    mfc1(kScratchReg, kDoubleCompareReg);
+    LoadZeroIfConditionNotZero(dest, kScratchReg);
+  } else {
+    Movt(dest, zero_reg);
+  }
+}
+
+void TurboAssembler::LoadZeroIfNotFPUCondition(Register dest) {
+  if (IsMipsArchVariant(kMips32r6)) {
+    mfc1(kScratchReg, kDoubleCompareReg);
+    LoadZeroIfConditionZero(dest, kScratchReg);
+  } else {
+    Movf(dest, zero_reg);
+  }
+}
+
 void TurboAssembler::Movz(Register rd, Register rs, Register rt) {
   if (IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r6)) {
     Label done;

src/mips/macro-assembler-mips.h

@@ -568,6 +568,9 @@ class TurboAssembler : public Assembler {
   void Movt(Register rd, Register rs, uint16_t cc = 0);
   void Movf(Register rd, Register rs, uint16_t cc = 0);
 
+  void LoadZeroIfFPUCondition(Register dest);
+  void LoadZeroIfNotFPUCondition(Register dest);
+
   void LoadZeroIfConditionNotZero(Register dest, Register condition);
   void LoadZeroIfConditionZero(Register dest, Register condition);
   void LoadZeroOnCondition(Register rd, Register rs, const Operand& rt,

src/mips64/macro-assembler-mips64.cc

@@ -2942,6 +2942,24 @@ void TurboAssembler::LoadZeroIfConditionZero(Register dest,
   }
 }
 
+void TurboAssembler::LoadZeroIfFPUCondition(Register dest) {
+  if (kArchVariant == kMips64r6) {
+    dmfc1(kScratchReg, kDoubleCompareReg);
+    LoadZeroIfConditionNotZero(dest, kScratchReg);
+  } else {
+    Movt(dest, zero_reg);
+  }
+}
+
+void TurboAssembler::LoadZeroIfNotFPUCondition(Register dest) {
+  if (kArchVariant == kMips64r6) {
+    dmfc1(kScratchReg, kDoubleCompareReg);
+    LoadZeroIfConditionZero(dest, kScratchReg);
+  } else {
+    Movf(dest, zero_reg);
+  }
+}
+
 void TurboAssembler::Movt(Register rd, Register rs, uint16_t cc) {
   movt(rd, rs, cc);
 }

src/mips64/macro-assembler-mips64.h

@@ -599,6 +599,9 @@ class TurboAssembler : public Assembler {
   void Movt(Register rd, Register rs, uint16_t cc = 0);
   void Movf(Register rd, Register rs, uint16_t cc = 0);
 
+  void LoadZeroIfFPUCondition(Register dest);
+  void LoadZeroIfNotFPUCondition(Register dest);
+
   void LoadZeroIfConditionNotZero(Register dest, Register condition);
   void LoadZeroIfConditionZero(Register dest, Register condition);
   void LoadZeroOnCondition(Register rd, Register rs, const Operand& rt,

src/wasm/baseline/mips/liftoff-assembler-mips.h

@@ -962,9 +962,9 @@ void LiftoffAssembler::emit_f32_set_cond(Condition cond, Register dst,
   FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
   TurboAssembler::CompareF32(fcond, lhs, rhs);
   if (predicate) {
-    TurboAssembler::Movf(dst, zero_reg);
+    TurboAssembler::LoadZeroIfNotFPUCondition(dst);
   } else {
-    TurboAssembler::Movt(dst, zero_reg);
+    TurboAssembler::LoadZeroIfFPUCondition(dst);
   }
 
   bind(&cont);
@@ -991,9 +991,9 @@ void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst,
   FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
   TurboAssembler::CompareF64(fcond, lhs, rhs);
   if (predicate) {
-    TurboAssembler::Movf(dst, zero_reg);
+    TurboAssembler::LoadZeroIfNotFPUCondition(dst);
   } else {
-    TurboAssembler::Movt(dst, zero_reg);
+    TurboAssembler::LoadZeroIfFPUCondition(dst);
   }
 
   bind(&cont);

src/wasm/baseline/mips64/liftoff-assembler-mips64.h

@@ -755,9 +755,9 @@ void LiftoffAssembler::emit_f32_set_cond(Condition cond, Register dst,
   FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
   TurboAssembler::CompareF32(fcond, lhs, rhs);
   if (predicate) {
-    TurboAssembler::Movf(dst, zero_reg);
+    TurboAssembler::LoadZeroIfNotFPUCondition(dst);
   } else {
-    TurboAssembler::Movt(dst, zero_reg);
+    TurboAssembler::LoadZeroIfFPUCondition(dst);
   }
 
   bind(&cont);
@@ -784,9 +784,9 @@ void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst,
   FPUCondition fcond = liftoff::ConditionToConditionCmpFPU(predicate, cond);
   TurboAssembler::CompareF64(fcond, lhs, rhs);
   if (predicate) {
-    TurboAssembler::Movf(dst, zero_reg);
+    TurboAssembler::LoadZeroIfNotFPUCondition(dst);
   } else {
-    TurboAssembler::Movt(dst, zero_reg);
+    TurboAssembler::LoadZeroIfFPUCondition(dst);
   }
 
   bind(&cont);