Commit 9f859fef authored by lrn@chromium.org's avatar lrn@chromium.org

Make X64 double-to-int32 conversion use the 64-bit version of cvttsd2si.

Use type info to allow ia32 to use the 32-bit versions in some cases.
Remove sse3-specific code from X64 GenericBinaryOpStub.

Review URL: http://codereview.chromium.org/1992011

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4632 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent fa7c92ea
......@@ -10296,6 +10296,11 @@ void IntegerConvert(MacroAssembler* masm,
Label done, right_exponent, normal_exponent;
Register scratch = ebx;
Register scratch2 = edi;
if (type_info.IsInteger32() && CpuFeatures::IsEnabled(SSE2)) {
CpuFeatures::Scope scope(SSE2);
__ cvttsd2si(ecx, FieldOperand(source, HeapNumber::kValueOffset));
return;
}
if (!type_info.IsInteger32() || !use_sse3) {
// Get exponent word.
__ mov(scratch, FieldOperand(source, HeapNumber::kExponentOffset));
......
......@@ -2510,6 +2510,17 @@ void Assembler::cvttsd2si(Register dst, const Operand& src) {
}
void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
emit(0xF2);
emit_rex_64(dst, src);
emit(0x0F);
emit(0x2C);
emit_sse_operand(dst, src);
}
void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
EnsureSpace ensure_space(this);
last_pc_ = pc_;
......
......@@ -1092,6 +1092,7 @@ class Assembler : public Malloced {
void cvttss2si(Register dst, const Operand& src);
void cvttsd2si(Register dst, const Operand& src);
void cvttsd2siq(Register dst, XMMRegister src);
void cvtlsi2sd(XMMRegister dst, const Operand& src);
void cvtlsi2sd(XMMRegister dst, Register src);
......
This diff is collapsed.
......@@ -713,7 +713,6 @@ class GenericBinaryOpStub: public CodeStub {
static_operands_type_(operands_type),
runtime_operands_type_(BinaryOpIC::DEFAULT),
name_(NULL) {
use_sse3_ = CpuFeatures::IsSupported(SSE3);
ASSERT(OpBits::is_valid(Token::NUM_TOKENS));
}
......@@ -723,7 +722,6 @@ class GenericBinaryOpStub: public CodeStub {
flags_(FlagBits::decode(key)),
args_in_registers_(ArgsInRegistersBits::decode(key)),
args_reversed_(ArgsReversedBits::decode(key)),
use_sse3_(SSE3Bits::decode(key)),
static_operands_type_(TypeInfo::ExpandedRepresentation(
StaticTypeInfoBits::decode(key))),
runtime_operands_type_(type_info),
......@@ -748,7 +746,6 @@ class GenericBinaryOpStub: public CodeStub {
GenericBinaryFlags flags_;
bool args_in_registers_; // Arguments passed in registers not on the stack.
bool args_reversed_; // Left and right argument are swapped.
bool use_sse3_;
// Number type information of operands, determined by code generator.
TypeInfo static_operands_type_;
......@@ -774,15 +771,14 @@ class GenericBinaryOpStub: public CodeStub {
}
#endif
// Minor key encoding in 18 bits TTNNNFRASOOOOOOOMM.
// Minor key encoding in 17 bits TTNNNFRAOOOOOOOMM.
class ModeBits: public BitField<OverwriteMode, 0, 2> {};
class OpBits: public BitField<Token::Value, 2, 7> {};
class SSE3Bits: public BitField<bool, 9, 1> {};
class ArgsInRegistersBits: public BitField<bool, 10, 1> {};
class ArgsReversedBits: public BitField<bool, 11, 1> {};
class FlagBits: public BitField<GenericBinaryFlags, 12, 1> {};
class StaticTypeInfoBits: public BitField<int, 13, 3> {};
class RuntimeTypeInfoBits: public BitField<BinaryOpIC::TypeInfo, 16, 2> {};
class ArgsInRegistersBits: public BitField<bool, 9, 1> {};
class ArgsReversedBits: public BitField<bool, 10, 1> {};
class FlagBits: public BitField<GenericBinaryFlags, 11, 1> {};
class StaticTypeInfoBits: public BitField<int, 12, 3> {};
class RuntimeTypeInfoBits: public BitField<BinaryOpIC::TypeInfo, 15, 2> {};
Major MajorKey() { return GenericBinaryOp; }
int MinorKey() {
......@@ -790,7 +786,6 @@ class GenericBinaryOpStub: public CodeStub {
return OpBits::encode(op_)
| ModeBits::encode(mode_)
| FlagBits::encode(flags_)
| SSE3Bits::encode(use_sse3_)
| ArgsInRegistersBits::encode(args_in_registers_)
| ArgsReversedBits::encode(args_reversed_)
| StaticTypeInfoBits::encode(
......
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