[regalloc] Add two spill modes.

This change adds two spilling modes: SpillAtDefinition and SpillDeferred.
The former is the known spilling mode where we spill at definition. The
latter spills only in deferred code regions. This is implemented based on
control flow aware allocation and its invariants.

The effect is mostly the same as splintering with the exception of
forward looking allocation decisions still being impacted by register
constraints in deferred code.

Change-Id: Ia708e5765dd095196a8127deb2d8bec950d37e04
Reviewed-on: https://chromium-review.googlesource.com/c/1437118Reviewed-by: Sigurd Schneider <sigurds@chromium.org>
Commit-Queue: Stephan Herhut <herhut@chromium.org>
Cr-Commit-Position: refs/heads/master@{#59759}

src/compiler/backend/instruction.h

@@ -976,6 +976,11 @@ class RpoNumber final {
     return other.index_ == this->index_ + 1;
   }
 
+  RpoNumber Next() const {
+    DCHECK(IsValid());
+    return RpoNumber(index_ + 1);
+  }
+
   // Comparison operators.
   bool operator==(RpoNumber other) const { return index_ == other.index_; }
   bool operator!=(RpoNumber other) const { return index_ != other.index_; }

src/compiler/backend/live-range-separator.cc

@@ -57,11 +57,11 @@ void CreateSplinter(TopLevelLiveRange* range, RegisterAllocationData* data,
 }
 
 void SetSlotUse(TopLevelLiveRange* range) {
-  range->set_has_slot_use(false);
+  range->reset_slot_use();
   for (const UsePosition* pos = range->first_pos();
        !range->has_slot_use() && pos != nullptr; pos = pos->next()) {
     if (pos->type() == UsePositionType::kRequiresSlot) {
-      range->set_has_slot_use(true);
+      range->register_slot_use(TopLevelLiveRange::SlotUseKind::kGeneralSlotUse);
     }
   }
 }

src/compiler/pipeline.cc

@@ -1721,6 +1721,14 @@ struct LocateSpillSlotsPhase {
   }
 };
 
+struct DecideSpillingModePhase {
+  static const char* phase_name() { return "decide spilling mode"; }
+
+  void Run(PipelineData* data, Zone* temp_zone) {
+    OperandAssigner assigner(data->register_allocation_data());
+    assigner.DecideSpillingMode();
+  }
+};
 
 struct AssignSpillSlotsPhase {
   static const char* phase_name() { return "assign spill slots"; }
@@ -2875,8 +2883,8 @@ void PipelineImpl::AllocateRegisters(const RegisterConfiguration* config,
     Run<MergeSplintersPhase>();
   }
 
+  Run<DecideSpillingModePhase>();
   Run<AssignSpillSlotsPhase>();
-
   Run<CommitAssignmentPhase>();
 
   // TODO(chromium:725559): remove this check once
@@ -2894,7 +2902,6 @@ void PipelineImpl::AllocateRegisters(const RegisterConfiguration* config,
   if (FLAG_turbo_move_optimization) {
     Run<OptimizeMovesPhase>();
   }
-
   Run<LocateSpillSlotsPhase>();
 
   TraceSequence(info(), data, "after register allocation");

src/flag-definitions.h

@@ -411,6 +411,8 @@ DEFINE_BOOL(turbo_preprocess_ranges, true,
             "run pre-register allocation heuristics")
 DEFINE_BOOL(turbo_control_flow_aware_allocation, false,
             "consider control flow while allocating registers")
+DEFINE_NEG_IMPLICATION(turbo_control_flow_aware_allocation,
+                       turbo_preprocess_ranges)
 
 DEFINE_STRING(turbo_filter, "*", "optimization filter for TurboFan compiler")
 DEFINE_BOOL(trace_turbo, false, "trace generated TurboFan IR")