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Commit 9658615e authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot
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[ia32] Merge some macro-assembler functions into macro lists 

Bug: v8:11384
Change-Id: I230548625908512753e5d05dcf4f19c593d9cb19
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2739449Reviewed-by: 's avatarBill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#73276}
parent 91775162
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Showing with 64 additions and 200 deletions
src/codegen/ia32/macro-assembler-ia32.cc
View file @ 9658615e
......@@ -2157,33 +2157,6 @@ void TurboAssembler::Cmpeqps(XMMRegister dst, XMMRegister src1,
}
}
void TurboAssembler::Pshufhw(XMMRegister dst, Operand src, uint8_t shuffle) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpshufhw(dst, src, shuffle);
} else {
pshufhw(dst, src, shuffle);
}
}
void TurboAssembler::Pshuflw(XMMRegister dst, Operand src, uint8_t shuffle) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpshuflw(dst, src, shuffle);
} else {
pshuflw(dst, src, shuffle);
}
}
void TurboAssembler::Pshufd(XMMRegister dst, Operand src, uint8_t shuffle) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpshufd(dst, src, shuffle);
} else {
pshufd(dst, src, shuffle);
}
}
void TurboAssembler::Psraw(XMMRegister dst, uint8_t shift) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
......@@ -2202,87 +2175,6 @@ void TurboAssembler::Psrlq(XMMRegister dst, uint8_t shift) {
}
}
void TurboAssembler::Psignb(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignb(dst, dst, src);
return;
}
if (CpuFeatures::IsSupported(SSSE3)) {
CpuFeatureScope sse_scope(this, SSSE3);
psignb(dst, src);
return;
}
FATAL("no AVX or SSE3 support");
}
void TurboAssembler::Psignw(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignw(dst, dst, src);
return;
}
if (CpuFeatures::IsSupported(SSSE3)) {
CpuFeatureScope sse_scope(this, SSSE3);
psignw(dst, src);
return;
}
FATAL("no AVX or SSE3 support");
}
void TurboAssembler::Psignd(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsignd(dst, dst, src);
return;
}
if (CpuFeatures::IsSupported(SSSE3)) {
CpuFeatureScope sse_scope(this, SSSE3);
psignd(dst, src);
return;
}
FATAL("no AVX or SSE3 support");
}
void TurboAssembler::Haddps(XMMRegister dst, XMMRegister src1, Operand src2) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vhaddps(dst, src1, src2);
} else {
CpuFeatureScope scope(this, SSE3);
DCHECK_EQ(dst, src1);
haddps(dst, src2);
}
}
void TurboAssembler::Pcmpeqq(XMMRegister dst, Operand src) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpcmpeqq(dst, dst, src);
} else {
CpuFeatureScope scope(this, SSE4_1);
pcmpeqq(dst, src);
}
}
void TurboAssembler::Pcmpeqq(XMMRegister dst, XMMRegister src1,
XMMRegister src2) {
Pcmpeqq(dst, src1, Operand(src2));
}
void TurboAssembler::Pcmpeqq(XMMRegister dst, XMMRegister src1, Operand src2) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpcmpeqq(dst, src1, src2);
} else {
// pcmpeqq is only used by Wasm SIMD, which requires SSE4_1.
DCHECK(CpuFeatures::IsSupported(SSE4_1));
CpuFeatureScope scope(this, SSE4_1);
DCHECK_EQ(dst, src1);
pcmpeqq(dst, src2);
}
}
void TurboAssembler::Pshufb(XMMRegister dst, XMMRegister src, Operand mask) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
......@@ -2327,58 +2219,6 @@ void TurboAssembler::Palignr(XMMRegister dst, Operand src, uint8_t imm8) {
FATAL("no AVX or SSE3 support");
}
void TurboAssembler::Pextrb(Operand dst, XMMRegister src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpextrb(dst, src, imm8);
return;
}
DCHECK(CpuFeatures::IsSupported(SSE4_1));
CpuFeatureScope sse_scope(this, SSE4_1);
pextrb(dst, src, imm8);
return;
}
void TurboAssembler::Pextrb(Register dst, XMMRegister src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpextrb(dst, src, imm8);
return;
}
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope sse_scope(this, SSE4_1);
pextrb(dst, src, imm8);
return;
}
FATAL("no AVX or SSE4.1 support");
}
void TurboAssembler::Pextrw(Operand dst, XMMRegister src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpextrw(dst, src, imm8);
return;
}
DCHECK(CpuFeatures::IsSupported(SSE4_1));
CpuFeatureScope sse_scope(this, SSE4_1);
pextrw(dst, src, imm8);
return;
}
void TurboAssembler::Pextrw(Register dst, XMMRegister src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpextrw(dst, src, imm8);
return;
}
if (CpuFeatures::IsSupported(SSE4_1)) {
CpuFeatureScope sse_scope(this, SSE4_1);
pextrw(dst, src, imm8);
return;
}
FATAL("no AVX or SSE4.1 support");
}
void TurboAssembler::Pextrd(Register dst, XMMRegister src, uint8_t imm8) {
if (imm8 == 0) {
Movd(dst, src);
......@@ -2493,17 +2333,6 @@ void TurboAssembler::Vbroadcastss(XMMRegister dst, Operand src) {
shufps(dst, dst, static_cast<byte>(0));
}
void TurboAssembler::Extractps(Operand dst, XMMRegister src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope avx_scope(this, AVX);
vextractps(dst, src, imm8);
}
DCHECK(CpuFeatures::IsSupported(SSE4_1));
CpuFeatureScope avx_scope(this, SSE4_1);
extractps(dst, src, imm8);
}
void TurboAssembler::Shufps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
......
src/codegen/ia32/macro-assembler-ia32.h
View file @ 9658615e
......@@ -302,21 +302,48 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
// Three-operand cmpeqps that moves src1 to dst if AVX is not supported.
void Cmpeqps(XMMRegister dst, XMMRegister src1, XMMRegister src2);
void Psraw(XMMRegister dst, uint8_t shift);
void Psrlq(XMMRegister dst, uint8_t shift);
void Pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
Pshufhw(dst, Operand(src), shuffle);
// Instructions whose SSE and AVX take the same number and type of operands.
#define AVX_OP3_WITH_TYPE(macro_name, name, dst_type, src1_type, src2_type) \
void macro_name(dst_type dst, src1_type src1, src2_type src2) { \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope scope(this, AVX); \
v##name(dst, src1, src2); \
} else { \
name(dst, src1, src2); \
} \
}
void Pshufhw(XMMRegister dst, Operand src, uint8_t shuffle);
void Pshuflw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
Pshuflw(dst, Operand(src), shuffle);
}
void Pshuflw(XMMRegister dst, Operand src, uint8_t shuffle);
void Pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
Pshufd(dst, Operand(src), shuffle);
AVX_OP3_WITH_TYPE(Pshufhw, pshufhw, XMMRegister, Operand, uint8_t)
AVX_OP3_WITH_TYPE(Pshufhw, pshufhw, XMMRegister, XMMRegister, uint8_t)
AVX_OP3_WITH_TYPE(Pshuflw, pshuflw, XMMRegister, Operand, uint8_t)
AVX_OP3_WITH_TYPE(Pshuflw, pshuflw, XMMRegister, XMMRegister, uint8_t)
AVX_OP3_WITH_TYPE(Pshufd, pshufd, XMMRegister, Operand, uint8_t)
AVX_OP3_WITH_TYPE(Pshufd, pshufd, XMMRegister, XMMRegister, uint8_t)
#undef AVX_OP3_WITH_TYPE
// Same as AVX_OP3_WITH_TYPE above but with SSE scope.
#define AVX_OP3_WITH_TYPE_SCOPE(macro_name, name, dst_type, src1_type, \
src2_type, sse_scope) \
void macro_name(dst_type dst, src1_type src1, src2_type src2) { \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope scope(this, AVX); \
v##name(dst, src1, src2); \
} else { \
CpuFeatureScope scope(this, sse_scope); \
name(dst, src1, src2); \
} \
}
void Pshufd(XMMRegister dst, Operand src, uint8_t shuffle);
void Psraw(XMMRegister dst, uint8_t shift);
void Psrlq(XMMRegister dst, uint8_t shift);
AVX_OP3_WITH_TYPE_SCOPE(Pextrb, pextrb, Operand, XMMRegister, uint8_t, SSE4_1)
AVX_OP3_WITH_TYPE_SCOPE(Pextrb, pextrb, Register, XMMRegister, uint8_t,
SSE4_1)
AVX_OP3_WITH_TYPE_SCOPE(Pextrw, pextrw, Operand, XMMRegister, uint8_t, SSE4_1)
AVX_OP3_WITH_TYPE_SCOPE(Pextrw, pextrw, Register, XMMRegister, uint8_t,
SSE4_1)
AVX_OP3_WITH_TYPE_SCOPE(Extractps, extractps, Operand, XMMRegister, uint8_t,
SSE4_1)
#undef AVX_OP3_WITH_TYPE_SCOPE
// SSE/SSE2 instructions with AVX version.
#define AVX_OP2_WITH_TYPE(macro_name, name, dst_type, src_type) \
......@@ -413,6 +440,29 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
#undef AVX_OP3_XO
#undef AVX_OP3_WITH_TYPE
// Same as AVX_OP3_WITH_TYPE but supports a CpuFeatureScope
#define AVX_OP2_WITH_TYPE_SCOPE(macro_name, name, dst_type, src_type, \
sse_scope) \
void macro_name(dst_type dst, src_type src) { \
if (CpuFeatures::IsSupported(AVX)) { \
CpuFeatureScope scope(this, AVX); \
v##name(dst, dst, src); \
} else if (CpuFeatures::IsSupported(sse_scope)) { \
CpuFeatureScope scope(this, sse_scope); \
name(dst, src); \
} \
}
#define AVX_OP2_XO(macro_name, name, sse_scope) \
AVX_OP2_WITH_TYPE_SCOPE(macro_name, name, XMMRegister, XMMRegister, \
sse_scope) \
AVX_OP2_WITH_TYPE_SCOPE(macro_name, name, XMMRegister, Operand, sse_scope)
AVX_OP2_XO(Psignb, psignb, SSSE3)
AVX_OP2_XO(Psignw, psignw, SSSE3)
AVX_OP2_XO(Psignd, psignd, SSSE3)
AVX_OP2_XO(Pcmpeqq, pcmpeqq, SSE4_1)
#undef AVX_OP2_XO
#undef AVX_OP2_WITH_TYPE_SCOPE
// Only use this macro when dst and src1 is the same in SSE case.
#define AVX_PACKED_OP3_WITH_TYPE(macro_name, name, dst_type, src_type) \
void macro_name(dst_type dst, dst_type src1, src_type src2) { \
......@@ -575,18 +625,15 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP3_WITH_TYPE_SCOPE(macro_name, name, XMMRegister, XMMRegister, SSE4_1) \
AVX_OP3_WITH_TYPE_SCOPE(macro_name, name, XMMRegister, Operand, SSE4_1)
AVX_OP3_WITH_TYPE_SCOPE(Haddps, haddps, XMMRegister, Operand, SSE3)
AVX_OP3_XO_SSE4(Pmaxsd, pmaxsd)
AVX_OP3_XO_SSE4(Pminsb, pminsb)
AVX_OP3_XO_SSE4(Pmaxsb, pmaxsb)
AVX_OP3_XO_SSE4(Pcmpeqq, pcmpeqq)
#undef AVX_OP3_XO_SSE4
#undef AVX_OP3_WITH_TYPE_SCOPE
void Haddps(XMMRegister dst, XMMRegister src1, Operand src2);
void Pcmpeqq(XMMRegister dst, Operand src);
void Pcmpeqq(XMMRegister dst, XMMRegister src) { Pcmpeqq(dst, Operand(src)); }
void Pcmpeqq(XMMRegister dst, XMMRegister src1, Operand src2);
void Pcmpeqq(XMMRegister dst, XMMRegister src1, XMMRegister src2);
void Pshufb(XMMRegister dst, XMMRegister src) { Pshufb(dst, dst, src); }
void Pshufb(XMMRegister dst, Operand src) { Pshufb(dst, dst, src); }
// Handles SSE and AVX. On SSE, moves src to dst if they are not equal.
......@@ -600,22 +647,11 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
}
void Pblendw(XMMRegister dst, Operand src, uint8_t imm8);
void Psignb(XMMRegister dst, XMMRegister src) { Psignb(dst, Operand(src)); }
void Psignb(XMMRegister dst, Operand src);
void Psignw(XMMRegister dst, XMMRegister src) { Psignw(dst, Operand(src)); }
void Psignw(XMMRegister dst, Operand src);
void Psignd(XMMRegister dst, XMMRegister src) { Psignd(dst, Operand(src)); }
void Psignd(XMMRegister dst, Operand src);
void Palignr(XMMRegister dst, XMMRegister src, uint8_t imm8) {
Palignr(dst, Operand(src), imm8);
}
void Palignr(XMMRegister dst, Operand src, uint8_t imm8);
void Pextrb(Operand dst, XMMRegister src, uint8_t imm8);
void Pextrb(Register dst, XMMRegister src, uint8_t imm8);
void Pextrw(Operand dst, XMMRegister src, uint8_t imm8);
void Pextrw(Register dst, XMMRegister src, uint8_t imm8);
void Pextrd(Register dst, XMMRegister src, uint8_t imm8);
void Pinsrb(XMMRegister dst, Register src, int8_t imm8) {
Pinsrb(dst, Operand(src), imm8);
......@@ -636,7 +672,6 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
// Moves src1 to dst if AVX is not supported.
void Pinsrw(XMMRegister dst, XMMRegister src1, Operand src2, int8_t imm8);
void Vbroadcastss(XMMRegister dst, Operand src);
void Extractps(Operand dst, XMMRegister src, uint8_t imm8);
// Shufps that will mov src1 into dst if AVX is not supported.
void Shufps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
......
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