Commit 94e1c858 authored by jyan's avatar jyan Committed by Commit bot

S390: Fix convertion from int32 to float32

Should use the same Mask code as float32 to int32

R=joransiu@ca.ibm.com, michael_dawson@ca.ibm.com, bjaideep@ca.ibm.com
BUG=

Review-Url: https://codereview.chromium.org/2160573003
Cr-Commit-Position: refs/heads/master@{#37871}
parent 5742da05
...@@ -1631,7 +1631,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -1631,7 +1631,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kS390_Float32ToInt32: { case kS390_Float32ToInt32: {
bool check_conversion = (i.OutputCount() > 1); bool check_conversion = (i.OutputCount() > 1);
__ ConvertFloat32ToInt32(i.InputDoubleRegister(0), i.OutputRegister(0), __ ConvertFloat32ToInt32(i.InputDoubleRegister(0), i.OutputRegister(0),
kScratchDoubleReg); kScratchDoubleReg, kRoundToZero);
if (check_conversion) { if (check_conversion) {
Label conversion_done; Label conversion_done;
__ LoadImmP(i.OutputRegister(1), Operand::Zero()); __ LoadImmP(i.OutputRegister(1), Operand::Zero());
......
...@@ -1406,7 +1406,6 @@ void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1, ...@@ -1406,7 +1406,6 @@ void Assembler::rrfe_form(Opcode op, Condition m3, Condition m4, Register r1,
RX_FORM_EMIT(bc, BC) RX_FORM_EMIT(bc, BC)
RR_FORM_EMIT(bctr, BCTR) RR_FORM_EMIT(bctr, BCTR)
RXE_FORM_EMIT(ceb, CEB) RXE_FORM_EMIT(ceb, CEB)
RRE_FORM_EMIT(cefbr, CEFBR)
SS1_FORM_EMIT(ed, ED) SS1_FORM_EMIT(ed, ED)
RX_FORM_EMIT(ex, EX) RX_FORM_EMIT(ex, EX)
RRE_FORM_EMIT(flogr, FLOGR) RRE_FORM_EMIT(flogr, FLOGR)
...@@ -2888,10 +2887,8 @@ void Assembler::celgbr(Condition m3, Condition m4, DoubleRegister r1, ...@@ -2888,10 +2887,8 @@ void Assembler::celgbr(Condition m3, Condition m4, DoubleRegister r1,
// Convert from Fixed Logical (F32<-32) // Convert from Fixed Logical (F32<-32)
void Assembler::celfbr(Condition m3, Condition m4, DoubleRegister r1, void Assembler::celfbr(Condition m3, Condition m4, DoubleRegister r1,
Register r2) { Register r2) {
DCHECK_EQ(m3, Condition(0));
DCHECK_EQ(m4, Condition(0)); DCHECK_EQ(m4, Condition(0));
rrfe_form(CELFBR, Condition(0), Condition(0), Register::from_code(r1.code()), rrfe_form(CELFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
r2);
} }
// Convert from Fixed Logical (L<-64) // Convert from Fixed Logical (L<-64)
...@@ -2911,8 +2908,8 @@ void Assembler::cdlfbr(Condition m3, Condition m4, DoubleRegister r1, ...@@ -2911,8 +2908,8 @@ void Assembler::cdlfbr(Condition m3, Condition m4, DoubleRegister r1,
} }
// Convert from Fixed point (S<-32) // Convert from Fixed point (S<-32)
void Assembler::cefbr(DoubleRegister r1, Register r2) { void Assembler::cefbr(Condition m3, DoubleRegister r1, Register r2) {
rre_form(CEFBR, Register::from_code(r1.code()), r2); rrfe_form(CEFBR, m3, Condition(0), Register::from_code(r1.code()), r2);
} }
// Convert to Fixed point (32<-S) // Convert to Fixed point (32<-S)
......
...@@ -765,7 +765,6 @@ class Assembler : public AssemblerBase { ...@@ -765,7 +765,6 @@ class Assembler : public AssemblerBase {
RRE_FORM(cdr); RRE_FORM(cdr);
RXE_FORM(cdb); RXE_FORM(cdb);
RXE_FORM(ceb); RXE_FORM(ceb);
RRE_FORM(cefbr);
RXE_FORM(ddb); RXE_FORM(ddb);
RRE_FORM(ddbr); RRE_FORM(ddbr);
SS1_FORM(ed); SS1_FORM(ed);
...@@ -1144,7 +1143,7 @@ class Assembler : public AssemblerBase { ...@@ -1144,7 +1143,7 @@ class Assembler : public AssemblerBase {
void cegbr(DoubleRegister fltReg, Register fixReg); void cegbr(DoubleRegister fltReg, Register fixReg);
void cdgbr(DoubleRegister fltReg, Register fixReg); void cdgbr(DoubleRegister fltReg, Register fixReg);
void cfebr(Condition m3, Register fixReg, DoubleRegister fltReg); void cfebr(Condition m3, Register fixReg, DoubleRegister fltReg);
void cefbr(DoubleRegister fltReg, Register fixReg); void cefbr(Condition m3, DoubleRegister fltReg, Register fixReg);
// Floating Point Compare Instructions // Floating Point Compare Instructions
void cebr(DoubleRegister r1, DoubleRegister r2); void cebr(DoubleRegister r1, DoubleRegister r2);
......
...@@ -913,6 +913,9 @@ bool Decoder::DecodeFourByte(Instruction* instr) { ...@@ -913,6 +913,9 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
case CEFBR: case CEFBR:
Format(instr, "cefbr\t'f5,'m2,'r6"); Format(instr, "cefbr\t'f5,'m2,'r6");
break; break;
case CELFBR:
Format(instr, "celfbr\t'f5,'m2,'r6");
break;
case CGEBR: case CGEBR:
Format(instr, "cgebr\t'r5,'m2,'f6"); Format(instr, "cgebr\t'r5,'m2,'f6");
break; break;
...@@ -937,6 +940,12 @@ bool Decoder::DecodeFourByte(Instruction* instr) { ...@@ -937,6 +940,12 @@ bool Decoder::DecodeFourByte(Instruction* instr) {
case CLFDBR: case CLFDBR:
Format(instr, "clfdbr\t'r5,'m2,'f6"); Format(instr, "clfdbr\t'r5,'m2,'f6");
break; break;
case CLFEBR:
Format(instr, "clfebr\t'r5,'m2,'f6");
break;
case CLGEBR:
Format(instr, "clgebr\t'r5,'m2,'f6");
break;
case CLGDBR: case CLGDBR:
Format(instr, "clgdbr\t'r5,'m2,'f6"); Format(instr, "clgdbr\t'r5,'m2,'f6");
break; break;
......
...@@ -656,12 +656,12 @@ void MacroAssembler::ConvertUnsignedIntToDouble(Register src, ...@@ -656,12 +656,12 @@ void MacroAssembler::ConvertUnsignedIntToDouble(Register src,
} }
void MacroAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) { void MacroAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
cefbr(dst, src); cefbr(Condition(4), dst, src);
} }
void MacroAssembler::ConvertUnsignedIntToFloat(Register src, void MacroAssembler::ConvertUnsignedIntToFloat(Register src,
DoubleRegister dst) { DoubleRegister dst) {
celfbr(Condition(0), Condition(0), dst, src); celfbr(Condition(4), Condition(0), dst, src);
} }
#if V8_TARGET_ARCH_S390X #if V8_TARGET_ARCH_S390X
...@@ -760,7 +760,7 @@ void MacroAssembler::ConvertFloat32ToInt32(const DoubleRegister double_input, ...@@ -760,7 +760,7 @@ void MacroAssembler::ConvertFloat32ToInt32(const DoubleRegister double_input,
m = Condition(5); m = Condition(5);
break; break;
case kRoundToNearest: case kRoundToNearest:
UNIMPLEMENTED(); m = Condition(4);
break; break;
case kRoundToPlusInf: case kRoundToPlusInf:
m = Condition(6); m = Condition(6);
...@@ -773,6 +773,10 @@ void MacroAssembler::ConvertFloat32ToInt32(const DoubleRegister double_input, ...@@ -773,6 +773,10 @@ void MacroAssembler::ConvertFloat32ToInt32(const DoubleRegister double_input,
break; break;
} }
cfebr(m, dst, double_input); cfebr(m, dst, double_input);
Label done;
b(Condition(0xe), &done, Label::kNear); // special case
LoadImmP(dst, Operand::Zero());
bind(&done);
ldgr(double_dst, dst); ldgr(double_dst, dst);
} }
...@@ -798,6 +802,10 @@ void MacroAssembler::ConvertFloat32ToUnsignedInt32( ...@@ -798,6 +802,10 @@ void MacroAssembler::ConvertFloat32ToUnsignedInt32(
break; break;
} }
clfebr(m, Condition(0), dst, double_input); clfebr(m, Condition(0), dst, double_input);
Label done;
b(Condition(0xe), &done, Label::kNear); // special case
LoadImmP(dst, Operand::Zero());
bind(&done);
ldgr(double_dst, dst); ldgr(double_dst, dst);
} }
......
...@@ -692,7 +692,7 @@ class MacroAssembler : public Assembler { ...@@ -692,7 +692,7 @@ class MacroAssembler : public Assembler {
void ConvertFloat32ToInt32(const DoubleRegister double_input, void ConvertFloat32ToInt32(const DoubleRegister double_input,
const Register dst, const Register dst,
const DoubleRegister double_dst, const DoubleRegister double_dst,
FPRoundingMode rounding_mode = kRoundToZero); FPRoundingMode rounding_mode);
void ConvertFloat32ToUnsignedInt32( void ConvertFloat32ToUnsignedInt32(
const DoubleRegister double_input, const Register dst, const DoubleRegister double_input, const Register dst,
const DoubleRegister double_dst, const DoubleRegister double_dst,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment