Commit 935e7f7b authored by palfia@homejinni.com's avatar palfia@homejinni.com

MIPS: Fixed faulty branch condition handling for doubles.

This commit also includes BranchF refactoring in macro-assembler.

TEST=mozilla/ecma/TypeConversion/9.2.js

BUG=

Review URL: https://codereview.chromium.org/12505004

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@13849 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent 922c22f0
...@@ -429,7 +429,9 @@ enum SecondaryField { ...@@ -429,7 +429,9 @@ enum SecondaryField {
// ----- Emulated conditions. // ----- Emulated conditions.
// On MIPS we use this enum to abstract from conditionnal branch instructions. // On MIPS we use this enum to abstract from conditionnal branch instructions.
// the 'U' prefix is used to specify unsigned comparisons. // The 'U' prefix is used to specify unsigned comparisons.
// Oppposite conditions must be paired as odd/even numbers
// because 'NegateCondition' function flips LSB to negate condition.
enum Condition { enum Condition {
// Any value < 0 is considered no_condition. // Any value < 0 is considered no_condition.
kNoCondition = -1, kNoCondition = -1,
...@@ -450,8 +452,10 @@ enum Condition { ...@@ -450,8 +452,10 @@ enum Condition {
greater_equal = 13, greater_equal = 13,
less_equal = 14, less_equal = 14,
greater = 15, greater = 15,
ueq = 16, // Unordered or Equal.
nue = 17, // Not (Unordered or Equal).
cc_always = 16, cc_always = 18,
// Aliases. // Aliases.
carry = Uless, carry = Uless,
......
...@@ -1826,7 +1826,7 @@ void LCodeGen::DoBranch(LBranch* instr) { ...@@ -1826,7 +1826,7 @@ void LCodeGen::DoBranch(LBranch* instr) {
CpuFeatureScope scope(masm(), FPU); CpuFeatureScope scope(masm(), FPU);
DoubleRegister reg = ToDoubleRegister(instr->value()); DoubleRegister reg = ToDoubleRegister(instr->value());
// Test the double value. Zero and NaN are false. // Test the double value. Zero and NaN are false.
EmitBranchF(true_block, false_block, ne, reg, kDoubleRegZero); EmitBranchF(true_block, false_block, nue, reg, kDoubleRegZero);
} else { } else {
ASSERT(r.IsTagged()); ASSERT(r.IsTagged());
Register reg = ToRegister(instr->value()); Register reg = ToRegister(instr->value());
......
...@@ -1125,23 +1125,19 @@ void MacroAssembler::BranchF(Label* target, ...@@ -1125,23 +1125,19 @@ void MacroAssembler::BranchF(Label* target,
// have been handled by the caller. // have been handled by the caller.
// Unsigned conditions are treated as their signed counterpart. // Unsigned conditions are treated as their signed counterpart.
switch (cc) { switch (cc) {
case Uless: case lt:
case less:
c(OLT, D, cmp1, cmp2); c(OLT, D, cmp1, cmp2);
bc1t(target); bc1t(target);
break; break;
case Ugreater: case gt:
case greater:
c(ULE, D, cmp1, cmp2); c(ULE, D, cmp1, cmp2);
bc1f(target); bc1f(target);
break; break;
case Ugreater_equal: case ge:
case greater_equal:
c(ULT, D, cmp1, cmp2); c(ULT, D, cmp1, cmp2);
bc1f(target); bc1f(target);
break; break;
case Uless_equal: case le:
case less_equal:
c(OLE, D, cmp1, cmp2); c(OLE, D, cmp1, cmp2);
bc1t(target); bc1t(target);
break; break;
...@@ -1149,10 +1145,18 @@ void MacroAssembler::BranchF(Label* target, ...@@ -1149,10 +1145,18 @@ void MacroAssembler::BranchF(Label* target,
c(EQ, D, cmp1, cmp2); c(EQ, D, cmp1, cmp2);
bc1t(target); bc1t(target);
break; break;
case ueq:
c(UEQ, D, cmp1, cmp2);
bc1t(target);
break;
case ne: case ne:
c(EQ, D, cmp1, cmp2); c(EQ, D, cmp1, cmp2);
bc1f(target); bc1f(target);
break; break;
case nue:
c(UEQ, D, cmp1, cmp2);
bc1f(target);
break;
default: default:
CHECK(0); CHECK(0);
}; };
......
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