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Commit 934443d9 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [liftoff]: Implement Add/Sub saturate ops 

Change-Id: If5f8aef98dcfbff14ba457669c4a5fba5c9226b8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3447376Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#79001}
parent 05643c76
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Showing with 163 additions and 130 deletions
src/codegen/s390/macro-assembler-s390.cc
View file @ 934443d9
......@@ -5787,6 +5787,95 @@ void TurboAssembler::I8x16UConvertI16x8(Simd128Register dst,
}
#undef VECTOR_PACK_UNSIGNED
#define BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, op, extract_high, \
extract_low, mode) \
DCHECK(dst != scratch1 && dst != scratch2); \
DCHECK(dst != src1 && dst != src2); \
extract_high(scratch1, src1, Condition(0), Condition(0), Condition(mode)); \
extract_high(scratch2, src2, Condition(0), Condition(0), Condition(mode)); \
op(dst, scratch1, scratch2, Condition(0), Condition(0), \
Condition(mode + 1)); \
extract_low(scratch1, src1, Condition(0), Condition(0), Condition(mode)); \
extract_low(scratch2, src2, Condition(0), Condition(0), Condition(mode)); \
op(scratch1, scratch1, scratch2, Condition(0), Condition(0), \
Condition(mode + 1));
void TurboAssembler::I16x8AddSatS(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 1)
vpks(dst, dst, scratch1, Condition(0), Condition(2));
}
void TurboAssembler::I16x8SubSatS(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 1)
vpks(dst, dst, scratch1, Condition(0), Condition(2));
}
void TurboAssembler::I16x8AddSatU(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 1)
vpkls(dst, dst, scratch1, Condition(0), Condition(2));
}
void TurboAssembler::I16x8SubSatU(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 1)
// negative intermediate values to 0.
vx(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero, Condition(0), Condition(0),
Condition(0));
vmx(dst, kDoubleRegZero, dst, Condition(0), Condition(0), Condition(2));
vmx(scratch1, kDoubleRegZero, scratch1, Condition(0), Condition(0),
Condition(2));
vpkls(dst, dst, scratch1, Condition(0), Condition(2));
}
void TurboAssembler::I8x16AddSatS(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuph, vupl, 0)
vpks(dst, dst, scratch1, Condition(0), Condition(1));
}
void TurboAssembler::I8x16SubSatS(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuph, vupl, 0)
vpks(dst, dst, scratch1, Condition(0), Condition(1));
}
void TurboAssembler::I8x16AddSatU(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, va, vuplh, vupll, 0)
vpkls(dst, dst, scratch1, Condition(0), Condition(1));
}
void TurboAssembler::I8x16SubSatU(Simd128Register dst, Simd128Register src1,
Simd128Register src2,
Simd128Register scratch1,
Simd128Register scratch2) {
BINOP_EXTRACT(dst, src1, src2, scratch1, scratch2, vs, vuplh, vupll, 0)
// negative intermediate values to 0.
vx(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero, Condition(0), Condition(0),
Condition(0));
vmx(dst, kDoubleRegZero, dst, Condition(0), Condition(0), Condition(1));
vmx(scratch1, kDoubleRegZero, scratch1, Condition(0), Condition(0),
Condition(1));
vpkls(dst, dst, scratch1, Condition(0), Condition(1));
}
#undef BINOP_EXTRACT
// Vector LE Load and Transform instructions.
#ifdef V8_TARGET_BIG_ENDIAN
#define IS_BIG_ENDIAN true
......
src/codegen/s390/macro-assembler-s390.h
View file @ 934443d9
......@@ -1339,6 +1339,23 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
#undef PROTOTYPE_SIMD_QFM
#undef SIMD_QFM_LIST
#define SIMD_ADD_SUB_SAT_LIST(V) \
V(I16x8AddSatS) \
V(I16x8SubSatS) \
V(I16x8AddSatU) \
V(I16x8SubSatU) \
V(I8x16AddSatS) \
V(I8x16SubSatS) \
V(I8x16AddSatU) \
V(I8x16SubSatU)
#define PROTOTYPE_SIMD_ADD_SUB_SAT(name) \
void name(Simd128Register dst, Simd128Register src1, Simd128Register src2, \
Simd128Register scratch1, Simd128Register scratch2);
SIMD_ADD_SUB_SAT_LIST(PROTOTYPE_SIMD_ADD_SUB_SAT)
#undef PROTOTYPE_SIMD_ADD_SUB_SAT
#undef SIMD_ADD_SUB_SAT_LIST
// ---------------------------------------------------------------------------
// Pointer compression Support
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ 934443d9
......@@ -2798,6 +2798,27 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_QFM
#undef SIMD_QFM_LIST
#define SIMD_ADD_SUB_SAT_LIST(V) \
V(I16x8AddSatS) \
V(I16x8SubSatS) \
V(I16x8AddSatU) \
V(I16x8SubSatU) \
V(I8x16AddSatS) \
V(I8x16SubSatS) \
V(I8x16AddSatU) \
V(I8x16SubSatU)
#define EMIT_SIMD_ADD_SUB_SAT(name) \
case kS390_##name: { \
__ name(i.OutputSimd128Register(), i.InputSimd128Register(0), \
i.InputSimd128Register(1), kScratchDoubleReg, \
i.ToSimd128Register(instr->TempAt(0))); \
break; \
}
SIMD_ADD_SUB_SAT_LIST(EMIT_SIMD_ADD_SUB_SAT)
#undef EMIT_SIMD_ADD_SUB_SAT
#undef SIMD_ADD_SUB_SAT_LIST
// vector unary ops
case kS390_F32x4RecipApprox: {
__ mov(kScratchReg, Operand(1));
......@@ -2901,88 +2922,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1), kScratchDoubleReg);
break;
}
#define BINOP_EXTRACT(op, extract_high, extract_low, mode) \
Simd128Register src1 = i.InputSimd128Register(0); \
Simd128Register src2 = i.InputSimd128Register(1); \
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0)); \
Simd128Register tempFPReg2 = i.ToSimd128Register(instr->TempAt(1)); \
DCHECK_NE(src1, tempFPReg1); \
DCHECK_NE(src2, tempFPReg1); \
__ extract_high(kScratchDoubleReg, src1, Condition(0), Condition(0), \
Condition(mode)); \
__ extract_high(tempFPReg1, src2, Condition(0), Condition(0), \
Condition(mode)); \
__ op(kScratchDoubleReg, kScratchDoubleReg, tempFPReg1, Condition(0), \
Condition(0), Condition(mode + 1)); \
__ extract_low(tempFPReg1, src1, Condition(0), Condition(0), \
Condition(mode)); \
__ extract_low(tempFPReg2, src2, Condition(0), Condition(0), \
Condition(mode)); \
__ op(tempFPReg1, tempFPReg1, tempFPReg2, Condition(0), Condition(0), \
Condition(mode + 1));
case kS390_I16x8AddSatS: {
BINOP_EXTRACT(va, vuph, vupl, 1)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I16x8SubSatS: {
BINOP_EXTRACT(vs, vuph, vupl, 1)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I16x8AddSatU: {
BINOP_EXTRACT(va, vuplh, vupll, 1)
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I16x8SubSatU: {
BINOP_EXTRACT(vs, vuplh, vupll, 1)
// negative to 0
__ vx(tempFPReg2, tempFPReg2, tempFPReg2, Condition(0), Condition(0),
Condition(0));
__ vmx(kScratchDoubleReg, tempFPReg2, kScratchDoubleReg, Condition(0),
Condition(0), Condition(2));
__ vmx(tempFPReg1, tempFPReg2, tempFPReg1, Condition(0), Condition(0),
Condition(2));
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(2));
break;
}
case kS390_I8x16AddSatS: {
BINOP_EXTRACT(va, vuph, vupl, 0)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
case kS390_I8x16SubSatS: {
BINOP_EXTRACT(vs, vuph, vupl, 0)
__ vpks(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
case kS390_I8x16AddSatU: {
BINOP_EXTRACT(va, vuplh, vupll, 0)
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
case kS390_I8x16SubSatU: {
BINOP_EXTRACT(vs, vuplh, vupll, 0)
// negative to 0
__ vx(tempFPReg2, tempFPReg2, tempFPReg2, Condition(0), Condition(0),
Condition(0));
__ vmx(kScratchDoubleReg, tempFPReg2, kScratchDoubleReg, Condition(0),
Condition(0), Condition(1));
__ vmx(tempFPReg1, tempFPReg2, tempFPReg1, Condition(0), Condition(0),
Condition(1));
__ vpkls(i.OutputSimd128Register(), kScratchDoubleReg, tempFPReg1,
Condition(0), Condition(1));
break;
}
#undef BINOP_EXTRACT
case kS390_I8x16Shuffle: {
Simd128Register dst = i.OutputSimd128Register(),
src0 = i.InputSimd128Register(0),
......
src/wasm/baseline/s390/liftoff-assembler-s390.h
View file @ 934443d9
......@@ -2505,6 +2505,42 @@ SIMD_ALL_TRUE_LIST(EMIT_SIMD_ALL_TRUE)
#undef EMIT_SIMD_ALL_TRUE
#undef SIMD_ALL_TRUE_LIST
#define SIMD_ADD_SUB_SAT_LIST(V) \
V(i16x8_add_sat_s, I16x8AddSatS) \
V(i16x8_sub_sat_s, I16x8SubSatS) \
V(i16x8_add_sat_u, I16x8AddSatU) \
V(i16x8_sub_sat_u, I16x8SubSatU) \
V(i8x16_add_sat_s, I8x16AddSatS) \
V(i8x16_sub_sat_s, I8x16SubSatS) \
V(i8x16_add_sat_u, I8x16AddSatU) \
V(i8x16_sub_sat_u, I8x16SubSatU)
#define EMIT_SIMD_ADD_SUB_SAT(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, LiftoffRegister lhs, \
LiftoffRegister rhs) { \
Simd128Register src1 = lhs.fp(); \
Simd128Register src2 = rhs.fp(); \
Simd128Register dest = dst.fp(); \
/* lhs and rhs are unique based on their selection under liftoff-compiler \
* `EmitBinOp`. */ \
/* Make sure dst and temp are also unique. */ \
if (dest == src1 || dest == src2) { \
dest = \
GetUnusedRegister(kFpReg, LiftoffRegList::ForRegs(src1, src2)).fp(); \
} \
Simd128Register temp = \
GetUnusedRegister(kFpReg, LiftoffRegList::ForRegs(dest, src1, src2)) \
.fp(); \
op(dest, src1, src2, kScratchDoubleReg, temp); \
/* Original dst register needs to be populated. */ \
if (dest != dst.fp()) { \
vlr(dst.fp(), dest, Condition(0), Condition(0), Condition(0)); \
} \
}
SIMD_ADD_SUB_SAT_LIST(EMIT_SIMD_ADD_SUB_SAT)
#undef EMIT_SIMD_ADD_SUB_SAT
#undef SIMD_ADD_SUB_SAT_LIST
void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
Register offset_reg, uintptr_t offset_imm,
LoadType type,
......@@ -2579,30 +2615,6 @@ void LiftoffAssembler::emit_i16x8_bitmask(LiftoffRegister dst,
I16x8BitMask(dst.gp(), src.fp(), r0, kScratchDoubleReg);
}
void LiftoffAssembler::emit_i16x8_add_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8addsaturate_s");
}
void LiftoffAssembler::emit_i16x8_sub_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8subsaturate_s");
}
void LiftoffAssembler::emit_i16x8_sub_sat_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8subsaturate_u");
}
void LiftoffAssembler::emit_i16x8_add_sat_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i16x8addsaturate_u");
}
void LiftoffAssembler::emit_i16x8_extadd_pairwise_i8x16_s(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i16x8.extadd_pairwise_i8x16_s");
......@@ -2642,30 +2654,6 @@ void LiftoffAssembler::emit_i8x16_bitmask(LiftoffRegister dst,
I8x16BitMask(dst.gp(), src.fp(), r0, ip, kScratchDoubleReg);
}
void LiftoffAssembler::emit_i8x16_add_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16addsaturate_s");
}
void LiftoffAssembler::emit_i8x16_sub_sat_s(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16subsaturate_s");
}
void LiftoffAssembler::emit_i8x16_sub_sat_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16subsaturate_u");
}
void LiftoffAssembler::emit_i8x16_add_sat_u(LiftoffRegister dst,
LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kUnsupportedArchitecture, "emit_i8x16addsaturate_u");
}
void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,
const uint8_t imms[16]) {
bailout(kUnsupportedArchitecture, "emit_s128_const");
......
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