PPC [simd]: Implement FP rounding on Sim

LVX simulation is also added in this CL.

Change-Id: I9c827d979cdcd86216f0b089e3819d65d6fc45c3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2753767Reviewed-by: Milad Fa <mfarazma@redhat.com>
Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73354}

src/codegen/ppc/constants-ppc.h

@@ -2929,6 +2929,11 @@ class Instruction {
       PPC_XFX_OPCODE_LIST(OPCODE_CASES)
       return static_cast<Opcode>(opcode);
     }
+    opcode = extcode | BitField(10, 2);
+    switch (opcode) {
+      PPC_XX2_OPCODE_LIST(OPCODE_CASES)
+      return static_cast<Opcode>(opcode);
+    }
     opcode = extcode | BitField(10, 1);
     switch (opcode) {
       PPC_X_OPCODE_LIST(OPCODE_CASES)
@@ -2938,11 +2943,6 @@ class Instruction {
       PPC_EVX_OPCODE_LIST(OPCODE_CASES)
       return static_cast<Opcode>(opcode);
     }
-    opcode = extcode | BitField(10, 2);
-    switch (opcode) {
-      PPC_XX2_OPCODE_LIST(OPCODE_CASES)
-      return static_cast<Opcode>(opcode);
-    }
     opcode = extcode | BitField(9, 1);
     switch (opcode) {
       PPC_XO_OPCODE_LIST(OPCODE_CASES)

src/execution/ppc/simulator-ppc.cc

@@ -3857,6 +3857,15 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
       return;
     }
     // Vector instructions.
+    case LVX: {
+      DECODE_VX_INSTRUCTION(vrt, ra, rb, T)
+      intptr_t ra_val = ra == 0 ? 0 : get_register(ra);
+      intptr_t rb_val = get_register(rb);
+      intptr_t addr = (ra_val + rb_val) & 0xFFFFFFFFFFFFFFF0;
+      simdr_t* ptr = reinterpret_cast<simdr_t*>(addr);
+      set_simd_register(vrt, *ptr);
+      break;
+    }
     case STVX: {
       DECODE_VX_INSTRUCTION(vrs, ra, rb, S)
       intptr_t ra_val = ra == 0 ? 0 : get_register(ra);
@@ -4415,6 +4424,30 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
       break;
     }
 #undef VECTOR_ADD_SUB_SATURATE
+#define VECTOR_FP_ROUNDING(type, op)                       \
+  int t = instr->RTValue();                                \
+  int b = instr->RBValue();                                \
+  FOR_EACH_LANE(i, type) {                                 \
+    type b_val = get_simd_register_by_lane<type>(b, i);    \
+    set_simd_register_by_lane<type>(t, i, std::op(b_val)); \
+  }
+    case XVRDPIP: {
+      VECTOR_FP_ROUNDING(double, ceil)
+      break;
+    }
+    case XVRDPIM: {
+      VECTOR_FP_ROUNDING(double, floor)
+      break;
+    }
+    case XVRDPIZ: {
+      VECTOR_FP_ROUNDING(double, trunc)
+      break;
+    }
+    case XVRDPI: {
+      VECTOR_FP_ROUNDING(double, nearbyint)
+      break;
+    }
+#undef VECTOR_FP_ROUNDING
     case VSEL: {
       int vrt = instr->RTValue();
       int vra = instr->RAValue();