[mips][wasm-simd] F32x4Div for mips

Port 85e2dbb3

Change-Id: I59fbd2eb10469179def9bc6332543f5fc406d1c7
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1784417
Auto-Submit: Mu Tao <pamilty@gmail.com>
Reviewed-by: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Commit-Queue: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#63563}

src/compiler/backend/mips/code-generator-mips.cc

@@ -2066,6 +2066,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                 i.InputSimd128Register(1));
       break;
     }
+    case kMipsF32x4Div: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ fdiv_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputSimd128Register(1));
+      break;
+    }
     case kMipsF32x4Max: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ fmax_w(i.OutputSimd128Register(), i.InputSimd128Register(0),

src/compiler/backend/mips/instruction-codes-mips.h

@@ -165,6 +165,7 @@ namespace compiler {
   V(MipsF32x4AddHoriz)             \
   V(MipsF32x4Sub)                  \
   V(MipsF32x4Mul)                  \
+  V(MipsF32x4Div)                  \
   V(MipsF32x4Max)                  \
   V(MipsF32x4Min)                  \
   V(MipsF32x4Eq)                   \

src/compiler/backend/mips/instruction-scheduler-mips.cc

@@ -51,6 +51,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMipsF32x4Max:
     case kMipsF32x4Min:
     case kMipsF32x4Mul:
+    case kMipsF32x4Div:
     case kMipsF32x4Ne:
     case kMipsF32x4Neg:
     case kMipsF32x4RecipApprox:

src/compiler/backend/mips/instruction-selector-mips.cc

@@ -2054,6 +2054,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4AddHoriz, kMipsF32x4AddHoriz)           \
   V(F32x4Sub, kMipsF32x4Sub)                     \
   V(F32x4Mul, kMipsF32x4Mul)                     \
+  V(F32x4Div, kMipsF32x4Div)                     \
   V(F32x4Max, kMipsF32x4Max)                     \
   V(F32x4Min, kMipsF32x4Min)                     \
   V(F32x4Eq, kMipsF32x4Eq)                       \

src/compiler/backend/mips64/code-generator-mips64.cc

@@ -2181,6 +2181,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                 i.InputSimd128Register(1));
       break;
     }
+    case kMips64F32x4Div: {
+      CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
+      __ fdiv_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputSimd128Register(1));
+      break;
+    }
     case kMips64F32x4Max: {
       CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
       __ fmax_w(i.OutputSimd128Register(), i.InputSimd128Register(0),

src/compiler/backend/mips64/instruction-codes-mips64.h

@@ -195,6 +195,7 @@ namespace compiler {
   V(Mips64F32x4AddHoriz)                     \
   V(Mips64F32x4Sub)                          \
   V(Mips64F32x4Mul)                          \
+  V(Mips64F32x4Div)                          \
   V(Mips64F32x4Max)                          \
   V(Mips64F32x4Min)                          \
   V(Mips64F32x4Eq)                           \

src/compiler/backend/mips64/instruction-scheduler-mips64.cc

@@ -79,6 +79,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kMips64F32x4Max:
     case kMips64F32x4Min:
     case kMips64F32x4Mul:
+    case kMips64F32x4Div:
     case kMips64F32x4Ne:
     case kMips64F32x4Neg:
     case kMips64F32x4RecipApprox:

src/compiler/backend/mips64/instruction-selector-mips64.cc

@@ -2717,6 +2717,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F32x4AddHoriz, kMips64F32x4AddHoriz)           \
   V(F32x4Sub, kMips64F32x4Sub)                     \
   V(F32x4Mul, kMips64F32x4Mul)                     \
+  V(F32x4Div, kMips64F32x4Div)                     \
   V(F32x4Max, kMips64F32x4Max)                     \
   V(F32x4Min, kMips64F32x4Min)                     \
   V(F32x4Eq, kMips64F32x4Eq)                       \