s390: [wasm-simd] separate lanes for simd AllTrue opcodes

Change-Id: I88c43793b82256e9f37ffd54468fd0374fedd164
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2097025Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#66665}

src/compiler/backend/s390/code-generator-s390.cc

@@ -3767,21 +3767,36 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ locgr(Condition(8), dst, temp);
       break;
     }
-    case kS390_S1x2AllTrue:
-    case kS390_S1x4AllTrue:
-    case kS390_S1x8AllTrue:
+#define SIMD_ALL_TRUE(mode)                                                    \
+  Simd128Register src = i.InputSimd128Register(0);                             \
+  Register dst = i.OutputRegister();                                           \
+  Register temp = i.TempRegister(0);                                           \
+  __ lgfi(temp, Operand(1));                                                   \
+  __ xgr(dst, dst);                                                            \
+  __ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg, Condition(0), \
+        Condition(0), Condition(2));                                           \
+  __ vceq(kScratchDoubleReg, src, kScratchDoubleReg, Condition(0),             \
+          Condition(mode));                                                    \
+  __ vtm(kScratchDoubleReg, kScratchDoubleReg, Condition(0), Condition(0),     \
+         Condition(0));                                                        \
+  __ locgr(Condition(8), dst, temp);
+    case kS390_S1x2AllTrue: {
+      SIMD_ALL_TRUE(3)
+      break;
+    }
+    case kS390_S1x4AllTrue: {
+      SIMD_ALL_TRUE(2)
+      break;
+    }
+    case kS390_S1x8AllTrue: {
+      SIMD_ALL_TRUE(1)
+      break;
+    }
     case kS390_S1x16AllTrue: {
-      Simd128Register src = i.InputSimd128Register(0);
-      Register dst = i.OutputRegister();
-      Register temp = i.TempRegister(0);
-      __ lgfi(temp, Operand(1));
-      __ xgr(dst, dst);
-      __ vceq(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg,
-              Condition(0), Condition(2));
-      __ vtm(src, kScratchDoubleReg, Condition(0), Condition(0), Condition(0));
-      __ locgr(Condition(1), dst, temp);
+      SIMD_ALL_TRUE(0)
       break;
     }
+#undef SIMD_ALL_TRUE
     // vector bitwise ops
     case kS390_S128And: {
       Simd128Register dst = i.OutputSimd128Register();