MIPS: Fix byteswap operation on mipsr1

We are not allowed to use t0 and t1 as temporary registers in
macro assembler as they are allocatable. This CL fixes the
issue.

Change-Id: I328532e669b081e5215887b725b0b645a86d98b1
Reviewed-on: https://chromium-review.googlesource.com/951488
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Reviewed-by: Sreten Kovacevic <sreten.kovacevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#51773}

src/compiler/mips/instruction-selector-mips.cc

@@ -674,7 +674,7 @@ void InstructionSelector::VisitWord64ReverseBytes(Node* node) { UNREACHABLE(); }
 void InstructionSelector::VisitWord32ReverseBytes(Node* node) {
   MipsOperandGenerator g(this);
   Emit(kMipsByteSwap32, g.DefineAsRegister(node),
-       g.UseRegister(node->InputAt(0)));
+       g.UseUniqueRegister(node->InputAt(0)));
 }
 
 void InstructionSelector::VisitWord32Ctz(Node* node) {

src/mips/macro-assembler-mips.cc

@@ -912,8 +912,11 @@ void TurboAssembler::ByteSwapSigned(Register dest, Register src,
     wsbh(dest, src);
     rotr(dest, dest, 16);
   } else if (IsMipsArchVariant(kMips32r1) || IsMipsArchVariant(kLoongson)) {
-    Register tmp = t0;
-    Register tmp2 = t1;
+    Register tmp = at;
+    Register tmp2 = t8;
+    DCHECK(dest != src);
+    DCHECK(dest != tmp && dest != tmp2);
+    DCHECK(src != tmp && src != tmp2);
 
     andi(tmp2, src, 0xFF);
     sll(tmp2, tmp2, 24);
@@ -953,7 +956,7 @@ void TurboAssembler::ByteSwapUnsigned(Register dest, Register src,
     if (operand_size == 1) {
       sll(src, src, 24);
     } else {
-      Register tmp = t0;
+      Register tmp = at;
 
       andi(tmp, src, 0xFF00);
       sll(src, src, 24);