[arm64][cleanup] Remove redundant {Register::IsValid}

Just use the default {is_valid} method provided by RegisterBase.

Drive-by: Also rename {CPURegList::IsValid} to {CPURegList::is_valid}.

R=mstarzinger@chromium.org

Bug: v8:9810
Change-Id: Ia3bc3c477e6329d63ffd00bca59762d9a6cf2fcc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1916201
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64952}

src/codegen/arm64/assembler-arm64-inl.h

@@ -44,12 +44,12 @@ inline bool CPURegister::IsSameSizeAndType(const CPURegister& other) const {
 }
 
 inline bool CPURegister::IsZero() const {
-  DCHECK(IsValid());
+  DCHECK(is_valid());
   return IsRegister() && (reg_code_ == kZeroRegCode);
 }
 
 inline bool CPURegister::IsSP() const {
-  DCHECK(IsValid());
+  DCHECK(is_valid());
   return IsRegister() && (reg_code_ == kSPRegInternalCode);
 }
 
@@ -82,13 +82,13 @@ inline void CPURegList::Remove(const CPURegister& other1,
 }
 
 inline void CPURegList::Combine(int code) {
-  DCHECK(CPURegister::Create(code, size_, type_).IsValid());
+  DCHECK(CPURegister::Create(code, size_, type_).is_valid());
   list_ |= (1ULL << code);
-  DCHECK(IsValid());
+  DCHECK(is_valid());
 }
 
 inline void CPURegList::Remove(int code) {
-  DCHECK(CPURegister::Create(code, size_, type_).IsValid());
+  DCHECK(CPURegister::Create(code, size_, type_).is_valid());
   list_ &= ~(1ULL << code);
 }
 
@@ -261,7 +261,7 @@ Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
       shift_(NO_SHIFT),
       extend_(extend),
       shift_amount_(shift_amount) {
-  DCHECK(reg.IsValid());
+  DCHECK(reg.is_valid());
   DCHECK_LE(shift_amount, 4);
   DCHECK(!reg.IsSP());
 
@@ -287,11 +287,11 @@ bool Operand::IsImmediate() const {
 }
 
 bool Operand::IsShiftedRegister() const {
-  return reg_.IsValid() && (shift_ != NO_SHIFT);
+  return reg_.is_valid() && (shift_ != NO_SHIFT);
 }
 
 bool Operand::IsExtendedRegister() const {
-  return reg_.IsValid() && (extend_ != NO_EXTEND);
+  return reg_.is_valid() && (extend_ != NO_EXTEND);
 }
 
 bool Operand::IsZero() const {
@@ -782,7 +782,7 @@ void RelocInfo::WipeOut() {
 }
 
 LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
-  DCHECK(rt.IsValid());
+  DCHECK(rt.is_valid());
   if (rt.IsRegister()) {
     return rt.Is64Bits() ? LDR_x : LDR_w;
   } else {
@@ -804,7 +804,7 @@ LoadStoreOp Assembler::LoadOpFor(const CPURegister& rt) {
 }
 
 LoadStoreOp Assembler::StoreOpFor(const CPURegister& rt) {
-  DCHECK(rt.IsValid());
+  DCHECK(rt.is_valid());
   if (rt.IsRegister()) {
     return rt.Is64Bits() ? STR_x : STR_w;
   } else {

src/codegen/arm64/assembler-arm64.cc

@@ -216,7 +216,7 @@ bool AreAliased(const CPURegister& reg1, const CPURegister& reg2,
       number_of_valid_fpregs++;
       unique_fpregs |= regs[i].bit();
     } else {
-      DCHECK(!regs[i].IsValid());
+      DCHECK(!regs[i].is_valid());
     }
   }
 
@@ -236,44 +236,44 @@ bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2,
                         const CPURegister& reg3, const CPURegister& reg4,
                         const CPURegister& reg5, const CPURegister& reg6,
                         const CPURegister& reg7, const CPURegister& reg8) {
-  DCHECK(reg1.IsValid());
+  DCHECK(reg1.is_valid());
   bool match = true;
-  match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
-  match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
-  match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
-  match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
-  match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
-  match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);
-  match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1);
+  match &= !reg2.is_valid() || reg2.IsSameSizeAndType(reg1);
+  match &= !reg3.is_valid() || reg3.IsSameSizeAndType(reg1);
+  match &= !reg4.is_valid() || reg4.IsSameSizeAndType(reg1);
+  match &= !reg5.is_valid() || reg5.IsSameSizeAndType(reg1);
+  match &= !reg6.is_valid() || reg6.IsSameSizeAndType(reg1);
+  match &= !reg7.is_valid() || reg7.IsSameSizeAndType(reg1);
+  match &= !reg8.is_valid() || reg8.IsSameSizeAndType(reg1);
   return match;
 }
 
 bool AreSameFormat(const VRegister& reg1, const VRegister& reg2,
                    const VRegister& reg3, const VRegister& reg4) {
-  DCHECK(reg1.IsValid());
-  return (!reg2.IsValid() || reg2.IsSameFormat(reg1)) &&
-         (!reg3.IsValid() || reg3.IsSameFormat(reg1)) &&
-         (!reg4.IsValid() || reg4.IsSameFormat(reg1));
+  DCHECK(reg1.is_valid());
+  return (!reg2.is_valid() || reg2.IsSameFormat(reg1)) &&
+         (!reg3.is_valid() || reg3.IsSameFormat(reg1)) &&
+         (!reg4.is_valid() || reg4.IsSameFormat(reg1));
 }
 
 bool AreConsecutive(const VRegister& reg1, const VRegister& reg2,
                     const VRegister& reg3, const VRegister& reg4) {
-  DCHECK(reg1.IsValid());
-  if (!reg2.IsValid()) {
-    DCHECK(!reg3.IsValid() && !reg4.IsValid());
+  DCHECK(reg1.is_valid());
+  if (!reg2.is_valid()) {
+    DCHECK(!reg3.is_valid() && !reg4.is_valid());
     return true;
   } else if (reg2.code() != ((reg1.code() + 1) % kNumberOfVRegisters)) {
     return false;
   }
 
-  if (!reg3.IsValid()) {
-    DCHECK(!reg4.IsValid());
+  if (!reg3.is_valid()) {
+    DCHECK(!reg4.is_valid());
     return true;
   } else if (reg3.code() != ((reg2.code() + 1) % kNumberOfVRegisters)) {
     return false;
   }
 
-  if (!reg4.IsValid()) {
+  if (!reg4.is_valid()) {
     return true;
   } else if (reg4.code() != ((reg3.code() + 1) % kNumberOfVRegisters)) {
     return false;

src/codegen/arm64/macro-assembler-arm64.cc

@@ -1049,7 +1049,7 @@ void TurboAssembler::Push(const CPURegister& src0, const CPURegister& src1,
                           const CPURegister& src2, const CPURegister& src3) {
   DCHECK(AreSameSizeAndType(src0, src1, src2, src3));
 
-  int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid();
+  int count = 1 + src1.is_valid() + src2.is_valid() + src3.is_valid();
   int size = src0.SizeInBytes();
   DCHECK_EQ(0, (size * count) % 16);
 
@@ -1062,7 +1062,7 @@ void TurboAssembler::Push(const CPURegister& src0, const CPURegister& src1,
                           const CPURegister& src6, const CPURegister& src7) {
   DCHECK(AreSameSizeAndType(src0, src1, src2, src3, src4, src5, src6, src7));
 
-  int count = 5 + src5.IsValid() + src6.IsValid() + src6.IsValid();
+  int count = 5 + src5.is_valid() + src6.is_valid() + src6.is_valid();
   int size = src0.SizeInBytes();
   DCHECK_EQ(0, (size * count) % 16);
 
@@ -1076,9 +1076,9 @@ void TurboAssembler::Pop(const CPURegister& dst0, const CPURegister& dst1,
   // instruction, not even into the zero register.
   DCHECK(!AreAliased(dst0, dst1, dst2, dst3));
   DCHECK(AreSameSizeAndType(dst0, dst1, dst2, dst3));
-  DCHECK(dst0.IsValid());
+  DCHECK(dst0.is_valid());
 
-  int count = 1 + dst1.IsValid() + dst2.IsValid() + dst3.IsValid();
+  int count = 1 + dst1.is_valid() + dst2.is_valid() + dst3.is_valid();
   int size = dst0.SizeInBytes();
   DCHECK_EQ(0, (size * count) % 16);
 
@@ -1093,9 +1093,9 @@ void TurboAssembler::Pop(const CPURegister& dst0, const CPURegister& dst1,
   // instruction, not even into the zero register.
   DCHECK(!AreAliased(dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7));
   DCHECK(AreSameSizeAndType(dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7));
-  DCHECK(dst0.IsValid());
+  DCHECK(dst0.is_valid());
 
-  int count = 5 + dst5.IsValid() + dst6.IsValid() + dst7.IsValid();
+  int count = 5 + dst5.is_valid() + dst6.is_valid() + dst7.is_valid();
   int size = dst0.SizeInBytes();
   DCHECK_EQ(0, (size * count) % 16);
 

src/codegen/arm64/register-arm64.h

@@ -121,35 +121,34 @@ class CPURegister : public RegisterBase<CPURegister, kRegAfterLast> {
 
   RegisterType type() const { return reg_type_; }
   int SizeInBits() const {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
     return reg_size_;
   }
   int SizeInBytes() const {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
     DCHECK_EQ(SizeInBits() % 8, 0);
     return reg_size_ / 8;
   }
   bool Is8Bits() const {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
     return reg_size_ == 8;
   }
   bool Is16Bits() const {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
     return reg_size_ == 16;
   }
   bool Is32Bits() const {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
     return reg_size_ == 32;
   }
   bool Is64Bits() const {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
     return reg_size_ == 64;
   }
   bool Is128Bits() const {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
     return reg_size_ == 128;
   }
-  bool IsValid() const { return reg_type_ != kNoRegister; }
   bool IsNone() const { return reg_type_ == kNoRegister; }
   constexpr bool Is(const CPURegister& other) const {
     return Aliases(other) && (reg_size_ == other.reg_size_);
@@ -205,7 +204,6 @@ class CPURegister : public RegisterBase<CPURegister, kRegAfterLast> {
   bool IsSameSizeAndType(const CPURegister& other) const;
 
   bool is(const CPURegister& other) const { return Is(other); }
-  bool is_valid() const { return IsValid(); }
 
  protected:
   int reg_size_;
@@ -571,12 +569,12 @@ class V8_EXPORT_PRIVATE CPURegList {
         size_(reg0.SizeInBits()),
         type_(reg0.type()) {
     DCHECK(AreSameSizeAndType(reg0, regs...));
-    DCHECK(IsValid());
+    DCHECK(is_valid());
   }
 
   CPURegList(CPURegister::RegisterType type, int size, RegList list)
       : list_(list), size_(size), type_(type) {
-    DCHECK(IsValid());
+    DCHECK(is_valid());
   }
 
   CPURegList(CPURegister::RegisterType type, int size, int first_reg,
@@ -589,7 +587,7 @@ class V8_EXPORT_PRIVATE CPURegList {
     DCHECK(last_reg >= first_reg);
     list_ = (1ULL << (last_reg + 1)) - 1;
     list_ &= ~((1ULL << first_reg) - 1);
-    DCHECK(IsValid());
+    DCHECK(is_valid());
   }
 
   CPURegister::RegisterType type() const {
@@ -602,7 +600,7 @@ class V8_EXPORT_PRIVATE CPURegList {
 
   inline void set_list(RegList new_list) {
     list_ = new_list;
-    DCHECK(IsValid());
+    DCHECK(is_valid());
   }
 
   // Combine another CPURegList into this one. Registers that already exist in
@@ -688,7 +686,7 @@ class V8_EXPORT_PRIVATE CPURegList {
   int size_;
   CPURegister::RegisterType type_;
 
-  bool IsValid() const {
+  bool is_valid() const {
     constexpr RegList kValidRegisters{0x8000000ffffffff};
     constexpr RegList kValidVRegisters{0x0000000ffffffff};
     switch (type_) {

src/diagnostics/arm64/disasm-arm64.cc

@@ -3563,7 +3563,7 @@ void DisassemblingDecoder::ProcessOutput(Instruction* /*instr*/) {
 }
 
 void DisassemblingDecoder::AppendRegisterNameToOutput(const CPURegister& reg) {
-  DCHECK(reg.IsValid());
+  DCHECK(reg.is_valid());
   char reg_char;
 
   if (reg.IsRegister()) {

src/wasm/baseline/arm64/liftoff-assembler-arm64.h

@@ -103,7 +103,7 @@ inline MemOperand GetMemOp(LiftoffAssembler* assm,
   // immediate value (in 31 bits, interpreted as signed value).
   // If the offset is bigger, we always trap and this code is not reached.
   DCHECK(is_uint31(offset_imm));
-  if (offset.IsValid()) {
+  if (offset.is_valid()) {
     if (offset_imm == 0) return MemOperand(addr.X(), offset.W(), UXTW);
     Register tmp = temps->AcquireW();
     assm->Add(tmp, offset.W(), offset_imm);
@@ -925,14 +925,14 @@ void LiftoffAssembler::emit_cond_jump(Condition cond, Label* label,
                                       Register rhs) {
   switch (type) {
     case kWasmI32:
-      if (rhs.IsValid()) {
+      if (rhs.is_valid()) {
         Cmp(lhs.W(), rhs.W());
       } else {
         Cmp(lhs.W(), wzr);
       }
       break;
     case kWasmI64:
-      if (rhs.IsValid()) {
+      if (rhs.is_valid()) {
         Cmp(lhs.X(), rhs.X());
       } else {
         Cmp(lhs.X(), xzr);
@@ -1070,7 +1070,7 @@ void LiftoffAssembler::CallIndirect(wasm::FunctionSig* sig,
                                     Register target) {
   // For Arm64, we have more cache registers than wasm parameters. That means
   // that target will always be in a register.
-  DCHECK(target.IsValid());
+  DCHECK(target.is_valid());
   Call(target);
 }
 

test/cctest/test-assembler-arm64.cc

@@ -13337,24 +13337,24 @@ TEST(vreg) {
 TEST(isvalid) {
   // This test doesn't generate any code, but it verifies some invariants
   // related to IsValid().
-  CHECK(!NoReg.IsValid());
-  CHECK(!NoVReg.IsValid());
-  CHECK(!NoCPUReg.IsValid());
+  CHECK(!NoReg.is_valid());
+  CHECK(!NoVReg.is_valid());
+  CHECK(!NoCPUReg.is_valid());
 
-  CHECK(x0.IsValid());
-  CHECK(w0.IsValid());
-  CHECK(x30.IsValid());
-  CHECK(w30.IsValid());
-  CHECK(xzr.IsValid());
-  CHECK(wzr.IsValid());
+  CHECK(x0.is_valid());
+  CHECK(w0.is_valid());
+  CHECK(x30.is_valid());
+  CHECK(w30.is_valid());
+  CHECK(xzr.is_valid());
+  CHECK(wzr.is_valid());
 
-  CHECK(sp.IsValid());
-  CHECK(wsp.IsValid());
+  CHECK(sp.is_valid());
+  CHECK(wsp.is_valid());
 
-  CHECK(d0.IsValid());
-  CHECK(s0.IsValid());
-  CHECK(d31.IsValid());
-  CHECK(s31.IsValid());
+  CHECK(d0.is_valid());
+  CHECK(s0.is_valid());
+  CHECK(d31.is_valid());
+  CHECK(s31.is_valid());
 
   CHECK(x0.IsRegister());
   CHECK(w0.IsRegister());
@@ -13376,20 +13376,20 @@ TEST(isvalid) {
 
   // Test the same as before, but using CPURegister types. This shouldn't make
   // any difference.
-  CHECK(static_cast<CPURegister>(x0).IsValid());
-  CHECK(static_cast<CPURegister>(w0).IsValid());
-  CHECK(static_cast<CPURegister>(x30).IsValid());
-  CHECK(static_cast<CPURegister>(w30).IsValid());
-  CHECK(static_cast<CPURegister>(xzr).IsValid());
-  CHECK(static_cast<CPURegister>(wzr).IsValid());
-
-  CHECK(static_cast<CPURegister>(sp).IsValid());
-  CHECK(static_cast<CPURegister>(wsp).IsValid());
-
-  CHECK(static_cast<CPURegister>(d0).IsValid());
-  CHECK(static_cast<CPURegister>(s0).IsValid());
-  CHECK(static_cast<CPURegister>(d31).IsValid());
-  CHECK(static_cast<CPURegister>(s31).IsValid());
+  CHECK(static_cast<CPURegister>(x0).is_valid());
+  CHECK(static_cast<CPURegister>(w0).is_valid());
+  CHECK(static_cast<CPURegister>(x30).is_valid());
+  CHECK(static_cast<CPURegister>(w30).is_valid());
+  CHECK(static_cast<CPURegister>(xzr).is_valid());
+  CHECK(static_cast<CPURegister>(wzr).is_valid());
+
+  CHECK(static_cast<CPURegister>(sp).is_valid());
+  CHECK(static_cast<CPURegister>(wsp).is_valid());
+
+  CHECK(static_cast<CPURegister>(d0).is_valid());
+  CHECK(static_cast<CPURegister>(s0).is_valid());
+  CHECK(static_cast<CPURegister>(d31).is_valid());
+  CHECK(static_cast<CPURegister>(s31).is_valid());
 
   CHECK(static_cast<CPURegister>(x0).IsRegister());
   CHECK(static_cast<CPURegister>(w0).IsRegister());

test/cctest/test-utils-arm64.cc

@@ -291,7 +291,7 @@ void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) {
       // We should never write into sp here.
       CHECK(!xn.Is(sp));
       if (!xn.IsZero()) {
-        if (!first.IsValid()) {
+        if (!first.is_valid()) {
           // This is the first register we've hit, so construct the literal.
           __ Mov(xn, value);
           first = xn;
@@ -311,7 +311,7 @@ void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) {
   for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
     if (reg_list & (1ULL << i)) {
       VRegister dn = VRegister::Create(i, kDRegSizeInBits);
-      if (!first.IsValid()) {
+      if (!first.is_valid()) {
         // This is the first register we've hit, so construct the literal.
         __ Fmov(dn, value);
         first = dn;