Commit 886f6b33 authored by bbudge's avatar bbudge Committed by Commit bot

[arm] BitcastF32U32 uses float registers.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2050563002
Cr-Commit-Position: refs/heads/master@{#37017}
parent 7596b5c6
......@@ -1145,6 +1145,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vmov(i.OutputRegister(), i.InputFloat32Register(0));
DCHECK_EQ(LeaveCC, i.OutputSBit());
break;
case kArmVmovF32U32:
__ vmov(i.OutputFloat32Register(), i.InputRegister(0));
DCHECK_EQ(LeaveCC, i.OutputSBit());
break;
case kArmVmovLowU32F64:
__ VmovLow(i.OutputRegister(), i.InputFloat64Register(0));
DCHECK_EQ(LeaveCC, i.OutputSBit());
......
......@@ -93,6 +93,7 @@ namespace compiler {
V(ArmVcvtS32F64) \
V(ArmVcvtU32F64) \
V(ArmVmovU32F32) \
V(ArmVmovF32U32) \
V(ArmVmovLowU32F64) \
V(ArmVmovLowF64U32) \
V(ArmVmovHighU32F64) \
......
......@@ -95,6 +95,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kArmVcvtS32F64:
case kArmVcvtU32F64:
case kArmVmovU32F32:
case kArmVmovF32U32:
case kArmVmovLowU32F64:
case kArmVmovLowF64U32:
case kArmVmovHighU32F64:
......
......@@ -1211,20 +1211,14 @@ void InstructionSelector::VisitRoundFloat64ToInt32(Node* node) {
VisitRR(this, kArmVcvtS32F64, node);
}
void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) {
VisitRR(this, kArmVmovU32F32, node);
}
void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) {
ArmOperandGenerator g(this);
Emit(kArmVmovLowF64U32, g.DefineAsRegister(node),
ImmediateOperand(ImmediateOperand::INLINE, 0),
g.UseRegister(node->InputAt(0)));
VisitRR(this, kArmVmovF32U32, node);
}
void InstructionSelector::VisitFloat32Add(Node* node) {
ArmOperandGenerator g(this);
Float32BinopMatcher m(node);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment