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Commit 87238b71 authored by Clemens Hammacher's avatar Clemens Hammacher Committed by Commit Bot
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[assembler][ia32] Make all imm8 values unsigned 

Most were using uint8_t already, but some were declared as int8_t. This
CL consistently makes 8-bit immediates unsigned values.

R=titzer@chromium.org

Change-Id: I8f829486fb5ab1bf597b0be1eabc9b811543c3e3
Reviewed-on: https://chromium-review.googlesource.com/1220147Reviewed-by: 's avatarBen Titzer <titzer@chromium.org>
Commit-Queue: Clemens Hammacher <clemensh@chromium.org>
Cr-Commit-Position: refs/heads/master@{#55820}
parent daf1a349
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Showing with 87 additions and 88 deletions
src/ia32/assembler-ia32.cc
View file @ 87238b71
......@@ -2358,7 +2358,7 @@ void Assembler::maxps(XMMRegister dst, Operand src) {
emit_sse_operand(dst, src);
}
void Assembler::cmpps(XMMRegister dst, Operand src, int8_t cmp) {
void Assembler::cmpps(XMMRegister dst, Operand src, uint8_t cmp) {
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0xC2);
......@@ -2617,7 +2617,7 @@ void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
EMIT(imm8);
}
void Assembler::psllw(XMMRegister reg, int8_t shift) {
void Assembler::psllw(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2626,7 +2626,7 @@ void Assembler::psllw(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::pslld(XMMRegister reg, int8_t shift) {
void Assembler::pslld(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2635,7 +2635,7 @@ void Assembler::pslld(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::psrlw(XMMRegister reg, int8_t shift) {
void Assembler::psrlw(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2644,7 +2644,7 @@ void Assembler::psrlw(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::psrld(XMMRegister reg, int8_t shift) {
void Assembler::psrld(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2653,7 +2653,7 @@ void Assembler::psrld(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::psraw(XMMRegister reg, int8_t shift) {
void Assembler::psraw(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2662,7 +2662,7 @@ void Assembler::psraw(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::psrad(XMMRegister reg, int8_t shift) {
void Assembler::psrad(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2671,7 +2671,7 @@ void Assembler::psrad(XMMRegister reg, int8_t shift) {
EMIT(shift);
}
void Assembler::psllq(XMMRegister reg, int8_t shift) {
void Assembler::psllq(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2689,8 +2689,7 @@ void Assembler::psllq(XMMRegister dst, XMMRegister src) {
emit_sse_operand(dst, src);
}
void Assembler::psrlq(XMMRegister reg, int8_t shift) {
void Assembler::psrlq(XMMRegister reg, uint8_t shift) {
EnsureSpace ensure_space(this);
EMIT(0x66);
EMIT(0x0F);
......@@ -2757,7 +2756,7 @@ void Assembler::palignr(XMMRegister dst, Operand src, uint8_t mask) {
EMIT(mask);
}
void Assembler::pextrb(Operand dst, XMMRegister src, int8_t offset) {
void Assembler::pextrb(Operand dst, XMMRegister src, uint8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2768,7 +2767,7 @@ void Assembler::pextrb(Operand dst, XMMRegister src, int8_t offset) {
EMIT(offset);
}
void Assembler::pextrw(Operand dst, XMMRegister src, int8_t offset) {
void Assembler::pextrw(Operand dst, XMMRegister src, uint8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2779,7 +2778,7 @@ void Assembler::pextrw(Operand dst, XMMRegister src, int8_t offset) {
EMIT(offset);
}
void Assembler::pextrd(Operand dst, XMMRegister src, int8_t offset) {
void Assembler::pextrd(Operand dst, XMMRegister src, uint8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2790,7 +2789,7 @@ void Assembler::pextrd(Operand dst, XMMRegister src, int8_t offset) {
EMIT(offset);
}
void Assembler::insertps(XMMRegister dst, Operand src, int8_t offset) {
void Assembler::insertps(XMMRegister dst, Operand src, uint8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2801,7 +2800,7 @@ void Assembler::insertps(XMMRegister dst, Operand src, int8_t offset) {
EMIT(offset);
}
void Assembler::pinsrb(XMMRegister dst, Operand src, int8_t offset) {
void Assembler::pinsrb(XMMRegister dst, Operand src, uint8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2812,7 +2811,7 @@ void Assembler::pinsrb(XMMRegister dst, Operand src, int8_t offset) {
EMIT(offset);
}
void Assembler::pinsrw(XMMRegister dst, Operand src, int8_t offset) {
void Assembler::pinsrw(XMMRegister dst, Operand src, uint8_t offset) {
DCHECK(is_uint8(offset));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2822,7 +2821,7 @@ void Assembler::pinsrw(XMMRegister dst, Operand src, int8_t offset) {
EMIT(offset);
}
void Assembler::pinsrd(XMMRegister dst, Operand src, int8_t offset) {
void Assembler::pinsrd(XMMRegister dst, Operand src, uint8_t offset) {
DCHECK(IsEnabled(SSE4_1));
EnsureSpace ensure_space(this);
EMIT(0x66);
......@@ -2933,7 +2932,7 @@ void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) {
}
void Assembler::vcmpps(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t cmp) {
uint8_t cmp) {
vps(0xC2, dst, src1, src2);
EMIT(cmp);
}
......@@ -2945,37 +2944,37 @@ void Assembler::vshufps(XMMRegister dst, XMMRegister src1, Operand src2,
EMIT(imm8);
}
void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8) {
void Assembler::vpsllw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(6);
vinstr(0x71, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpslld(XMMRegister dst, XMMRegister src, int8_t imm8) {
void Assembler::vpslld(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(6);
vinstr(0x72, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int8_t imm8) {
void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(2);
vinstr(0x71, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int8_t imm8) {
void Assembler::vpsrld(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(2);
vinstr(0x72, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int8_t imm8) {
void Assembler::vpsraw(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(4);
vinstr(0x71, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
}
void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int8_t imm8) {
void Assembler::vpsrad(XMMRegister dst, XMMRegister src, uint8_t imm8) {
XMMRegister iop = XMMRegister::from_code(4);
vinstr(0x72, iop, dst, Operand(src), k66, k0F, kWIG);
EMIT(imm8);
......@@ -3008,41 +3007,41 @@ void Assembler::vpalignr(XMMRegister dst, XMMRegister src1, Operand src2,
EMIT(mask);
}
void Assembler::vpextrb(Operand dst, XMMRegister src, int8_t offset) {
void Assembler::vpextrb(Operand dst, XMMRegister src, uint8_t offset) {
vinstr(0x14, src, xmm0, dst, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpextrw(Operand dst, XMMRegister src, int8_t offset) {
void Assembler::vpextrw(Operand dst, XMMRegister src, uint8_t offset) {
vinstr(0x15, src, xmm0, dst, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpextrd(Operand dst, XMMRegister src, int8_t offset) {
void Assembler::vpextrd(Operand dst, XMMRegister src, uint8_t offset) {
vinstr(0x16, src, xmm0, dst, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vinsertps(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
uint8_t offset) {
vinstr(0x21, dst, src1, src2, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
uint8_t offset) {
vinstr(0x20, dst, src1, src2, k66, k0F3A, kWIG);
EMIT(offset);
}
void Assembler::vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
uint8_t offset) {
vinstr(0xC4, dst, src1, src2, k66, k0F, kWIG);
EMIT(offset);
}
void Assembler::vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset) {
uint8_t offset) {
vinstr(0x22, dst, src1, src2, k66, k0F3A, kWIG);
EMIT(offset);
}
......
src/ia32/assembler-ia32.h
View file @ 87238b71
......@@ -986,7 +986,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void maxps(XMMRegister dst, Operand src);
void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
void cmpps(XMMRegister dst, Operand src, int8_t cmp);
void cmpps(XMMRegister dst, Operand src, uint8_t cmp);
#define SSE_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src) { \
cmpps(dst, Operand(src), imm8); \
......@@ -1091,15 +1091,15 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
void extractps(Register dst, XMMRegister src, byte imm8);
void psllw(XMMRegister reg, int8_t shift);
void pslld(XMMRegister reg, int8_t shift);
void psrlw(XMMRegister reg, int8_t shift);
void psrld(XMMRegister reg, int8_t shift);
void psraw(XMMRegister reg, int8_t shift);
void psrad(XMMRegister reg, int8_t shift);
void psllq(XMMRegister reg, int8_t shift);
void psllw(XMMRegister reg, uint8_t shift);
void pslld(XMMRegister reg, uint8_t shift);
void psrlw(XMMRegister reg, uint8_t shift);
void psrld(XMMRegister reg, uint8_t shift);
void psraw(XMMRegister reg, uint8_t shift);
void psrad(XMMRegister reg, uint8_t shift);
void psllq(XMMRegister reg, uint8_t shift);
void psllq(XMMRegister dst, XMMRegister src);
void psrlq(XMMRegister reg, int8_t shift);
void psrlq(XMMRegister reg, uint8_t shift);
void psrlq(XMMRegister dst, XMMRegister src);
void pshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
......@@ -1125,36 +1125,36 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
}
void palignr(XMMRegister dst, Operand src, uint8_t mask);
void pextrb(Register dst, XMMRegister src, int8_t offset) {
void pextrb(Register dst, XMMRegister src, uint8_t offset) {
pextrb(Operand(dst), src, offset);
}
void pextrb(Operand dst, XMMRegister src, int8_t offset);
void pextrb(Operand dst, XMMRegister src, uint8_t offset);
// Use SSE4_1 encoding for pextrw reg, xmm, imm8 for consistency
void pextrw(Register dst, XMMRegister src, int8_t offset) {
void pextrw(Register dst, XMMRegister src, uint8_t offset) {
pextrw(Operand(dst), src, offset);
}
void pextrw(Operand dst, XMMRegister src, int8_t offset);
void pextrd(Register dst, XMMRegister src, int8_t offset) {
void pextrw(Operand dst, XMMRegister src, uint8_t offset);
void pextrd(Register dst, XMMRegister src, uint8_t offset) {
pextrd(Operand(dst), src, offset);
}
void pextrd(Operand dst, XMMRegister src, int8_t offset);
void pextrd(Operand dst, XMMRegister src, uint8_t offset);
void insertps(XMMRegister dst, XMMRegister src, int8_t offset) {
void insertps(XMMRegister dst, XMMRegister src, uint8_t offset) {
insertps(dst, Operand(src), offset);
}
void insertps(XMMRegister dst, Operand src, int8_t offset);
void pinsrb(XMMRegister dst, Register src, int8_t offset) {
void insertps(XMMRegister dst, Operand src, uint8_t offset);
void pinsrb(XMMRegister dst, Register src, uint8_t offset) {
pinsrb(dst, Operand(src), offset);
}
void pinsrb(XMMRegister dst, Operand src, int8_t offset);
void pinsrw(XMMRegister dst, Register src, int8_t offset) {
void pinsrb(XMMRegister dst, Operand src, uint8_t offset);
void pinsrw(XMMRegister dst, Register src, uint8_t offset) {
pinsrw(dst, Operand(src), offset);
}
void pinsrw(XMMRegister dst, Operand src, int8_t offset);
void pinsrd(XMMRegister dst, Register src, int8_t offset) {
void pinsrw(XMMRegister dst, Operand src, uint8_t offset);
void pinsrd(XMMRegister dst, Register src, uint8_t offset) {
pinsrd(dst, Operand(src), offset);
}
void pinsrd(XMMRegister dst, Operand src, int8_t offset);
void pinsrd(XMMRegister dst, Operand src, uint8_t offset);
// AVX instructions
void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
......@@ -1417,12 +1417,12 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
}
void vshufps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8);
void vpsllw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpslld(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrlw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrld(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsraw(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsrad(XMMRegister dst, XMMRegister src, int8_t imm8);
void vpsllw(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpslld(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsrlw(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsrld(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsraw(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpsrad(XMMRegister dst, XMMRegister src, uint8_t imm8);
void vpshufhw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
vpshufhw(dst, Operand(src), shuffle);
......@@ -1449,40 +1449,40 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
}
void vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask);
void vpextrb(Register dst, XMMRegister src, int8_t offset) {
void vpextrb(Register dst, XMMRegister src, uint8_t offset) {
vpextrb(Operand(dst), src, offset);
}
void vpextrb(Operand dst, XMMRegister src, int8_t offset);
void vpextrw(Register dst, XMMRegister src, int8_t offset) {
void vpextrb(Operand dst, XMMRegister src, uint8_t offset);
void vpextrw(Register dst, XMMRegister src, uint8_t offset) {
vpextrw(Operand(dst), src, offset);
}
void vpextrw(Operand dst, XMMRegister src, int8_t offset);
void vpextrd(Register dst, XMMRegister src, int8_t offset) {
void vpextrw(Operand dst, XMMRegister src, uint8_t offset);
void vpextrd(Register dst, XMMRegister src, uint8_t offset) {
vpextrd(Operand(dst), src, offset);
}
void vpextrd(Operand dst, XMMRegister src, int8_t offset);
void vpextrd(Operand dst, XMMRegister src, uint8_t offset);
void vinsertps(XMMRegister dst, XMMRegister src1, XMMRegister src2,
int8_t offset) {
uint8_t offset) {
vinsertps(dst, src1, Operand(src2), offset);
}
void vinsertps(XMMRegister dst, XMMRegister src1, Operand src2,
int8_t offset);
uint8_t offset);
void vpinsrb(XMMRegister dst, XMMRegister src1, Register src2,
int8_t offset) {
uint8_t offset) {
vpinsrb(dst, src1, Operand(src2), offset);
}
void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, int8_t offset);
void vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset);
void vpinsrw(XMMRegister dst, XMMRegister src1, Register src2,
int8_t offset) {
uint8_t offset) {
vpinsrw(dst, src1, Operand(src2), offset);
}
void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, int8_t offset);
void vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset);
void vpinsrd(XMMRegister dst, XMMRegister src1, Register src2,
int8_t offset) {
uint8_t offset) {
vpinsrd(dst, src1, Operand(src2), offset);
}
void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, int8_t offset);
void vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset);
void vcvtdq2ps(XMMRegister dst, XMMRegister src) {
vcvtdq2ps(dst, Operand(src));
......@@ -1615,7 +1615,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2);
void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, int8_t cmp);
void vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t cmp);
#define AVX_CMP_P(instr, imm8) \
void instr##ps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { \
vcmpps(dst, src1, Operand(src2), imm8); \
......
src/ia32/macro-assembler-ia32.cc
View file @ 87238b71
......@@ -1364,7 +1364,7 @@ void TurboAssembler::Pshufd(XMMRegister dst, Operand src, uint8_t shuffle) {
}
}
void TurboAssembler::Psraw(XMMRegister dst, int8_t shift) {
void TurboAssembler::Psraw(XMMRegister dst, uint8_t shift) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsraw(dst, dst, shift);
......@@ -1373,7 +1373,7 @@ void TurboAssembler::Psraw(XMMRegister dst, int8_t shift) {
}
}
void TurboAssembler::Psrlw(XMMRegister dst, int8_t shift) {
void TurboAssembler::Psrlw(XMMRegister dst, uint8_t shift) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpsrlw(dst, dst, shift);
......@@ -1466,7 +1466,7 @@ void TurboAssembler::Palignr(XMMRegister dst, Operand src, uint8_t imm8) {
FATAL("no AVX or SSE3 support");
}
void TurboAssembler::Pextrb(Register dst, XMMRegister src, int8_t imm8) {
void TurboAssembler::Pextrb(Register dst, XMMRegister src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpextrb(dst, src, imm8);
......@@ -1480,7 +1480,7 @@ void TurboAssembler::Pextrb(Register dst, XMMRegister src, int8_t imm8) {
FATAL("no AVX or SSE4.1 support");
}
void TurboAssembler::Pextrw(Register dst, XMMRegister src, int8_t imm8) {
void TurboAssembler::Pextrw(Register dst, XMMRegister src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpextrw(dst, src, imm8);
......@@ -1494,7 +1494,7 @@ void TurboAssembler::Pextrw(Register dst, XMMRegister src, int8_t imm8) {
FATAL("no AVX or SSE4.1 support");
}
void TurboAssembler::Pextrd(Register dst, XMMRegister src, int8_t imm8) {
void TurboAssembler::Pextrd(Register dst, XMMRegister src, uint8_t imm8) {
if (imm8 == 0) {
Movd(dst, src);
return;
......@@ -1519,7 +1519,7 @@ void TurboAssembler::Pextrd(Register dst, XMMRegister src, int8_t imm8) {
add(esp, Immediate(kDoubleSize));
}
void TurboAssembler::Pinsrd(XMMRegister dst, Operand src, int8_t imm8) {
void TurboAssembler::Pinsrd(XMMRegister dst, Operand src, uint8_t imm8) {
if (CpuFeatures::IsSupported(AVX)) {
CpuFeatureScope scope(this, AVX);
vpinsrd(dst, dst, src, imm8);
......
src/ia32/macro-assembler-ia32.h
View file @ 87238b71
......@@ -288,8 +288,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
Pshufd(dst, Operand(src), shuffle);
}
void Pshufd(XMMRegister dst, Operand src, uint8_t shuffle);
void Psraw(XMMRegister dst, int8_t shift);
void Psrlw(XMMRegister dst, int8_t shift);
void Psraw(XMMRegister dst, uint8_t shift);
void Psrlw(XMMRegister dst, uint8_t shift);
// SSE/SSE2 instructions with AVX version.
#define AVX_OP2_WITH_TYPE(macro_name, name, dst_type, src_type) \
......@@ -398,13 +398,13 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
}
void Palignr(XMMRegister dst, Operand src, uint8_t imm8);
void Pextrb(Register dst, XMMRegister src, int8_t imm8);
void Pextrw(Register dst, XMMRegister src, int8_t imm8);
void Pextrd(Register dst, XMMRegister src, int8_t imm8);
void Pinsrd(XMMRegister dst, Register src, int8_t imm8) {
void Pextrb(Register dst, XMMRegister src, uint8_t imm8);
void Pextrw(Register dst, XMMRegister src, uint8_t imm8);
void Pextrd(Register dst, XMMRegister src, uint8_t imm8);
void Pinsrd(XMMRegister dst, Register src, uint8_t imm8) {
Pinsrd(dst, Operand(src), imm8);
}
void Pinsrd(XMMRegister dst, Operand src, int8_t imm8);
void Pinsrd(XMMRegister dst, Operand src, uint8_t imm8);
// Expression support
// cvtsi2sd instruction only writes to the low 64-bit of dst register, which
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