[wasm-simd][arm64] Implement integer absolute

Implements i8x16.abs, i16x8.abs, and i32x4.abs.

Bug: v8:10233
Change-Id: I350ceca7ee75037615985ea955c5f17997996aac
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2067842
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66442}

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -2130,6 +2130,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       SIMD_BINOP_CASE(kArm64I32x4MaxU, Umax, 4S);
       SIMD_BINOP_CASE(kArm64I32x4GtU, Cmhi, 4S);
       SIMD_BINOP_CASE(kArm64I32x4GeU, Cmhs, 4S);
+      SIMD_UNOP_CASE(kArm64I32x4Abs, Abs, 4S);
     case kArm64I16x8Splat: {
       __ Dup(i.OutputSimd128Register().V8H(), i.InputRegister32(0));
       break;
@@ -2230,6 +2231,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       SIMD_BINOP_CASE(kArm64I16x8GtU, Cmhi, 8H);
       SIMD_BINOP_CASE(kArm64I16x8GeU, Cmhs, 8H);
       SIMD_BINOP_CASE(kArm64I16x8RoundingAverageU, Urhadd, 8H);
+      SIMD_UNOP_CASE(kArm64I16x8Abs, Abs, 8H);
     case kArm64I8x16Splat: {
       __ Dup(i.OutputSimd128Register().V16B(), i.InputRegister32(0));
       break;
@@ -2318,6 +2320,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       SIMD_BINOP_CASE(kArm64I8x16GtU, Cmhi, 16B);
       SIMD_BINOP_CASE(kArm64I8x16GeU, Cmhs, 16B);
       SIMD_BINOP_CASE(kArm64I8x16RoundingAverageU, Urhadd, 16B);
+      SIMD_UNOP_CASE(kArm64I8x16Abs, Abs, 16B);
     case kArm64S128Zero: {
       __ Movi(i.OutputSimd128Register().V16B(), 0);
       break;

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -252,6 +252,7 @@ namespace compiler {
   V(Arm64I32x4MaxU)                         \
   V(Arm64I32x4GtU)                          \
   V(Arm64I32x4GeU)                          \
+  V(Arm64I32x4Abs)                          \
   V(Arm64I16x8Splat)                        \
   V(Arm64I16x8ExtractLaneU)                 \
   V(Arm64I16x8ExtractLaneS)                 \
@@ -285,6 +286,7 @@ namespace compiler {
   V(Arm64I16x8GtU)                          \
   V(Arm64I16x8GeU)                          \
   V(Arm64I16x8RoundingAverageU)             \
+  V(Arm64I16x8Abs)                          \
   V(Arm64I8x16Splat)                        \
   V(Arm64I8x16ExtractLaneU)                 \
   V(Arm64I8x16ExtractLaneS)                 \
@@ -313,6 +315,7 @@ namespace compiler {
   V(Arm64I8x16GtU)                          \
   V(Arm64I8x16GeU)                          \
   V(Arm64I8x16RoundingAverageU)             \
+  V(Arm64I8x16Abs)                          \
   V(Arm64S128Zero)                          \
   V(Arm64S128Dup)                           \
   V(Arm64S128And)                           \

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -222,6 +222,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64I32x4MaxU:
     case kArm64I32x4GtU:
     case kArm64I32x4GeU:
+    case kArm64I32x4Abs:
     case kArm64I16x8Splat:
     case kArm64I16x8ExtractLaneU:
     case kArm64I16x8ExtractLaneS:
@@ -255,6 +256,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64I16x8GtU:
     case kArm64I16x8GeU:
     case kArm64I16x8RoundingAverageU:
+    case kArm64I16x8Abs:
     case kArm64I8x16Splat:
     case kArm64I8x16ExtractLaneU:
     case kArm64I8x16ExtractLaneS:
@@ -283,6 +285,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64I8x16GtU:
     case kArm64I8x16GeU:
     case kArm64I8x16RoundingAverageU:
+    case kArm64I8x16Abs:
     case kArm64S128Zero:
     case kArm64S128Dup:
     case kArm64S128And:

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -3167,12 +3167,15 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I32x4UConvertF32x4, kArm64I32x4UConvertF32x4)         \
   V(I32x4UConvertI16x8Low, kArm64I32x4UConvertI16x8Low)   \
   V(I32x4UConvertI16x8High, kArm64I32x4UConvertI16x8High) \
+  V(I32x4Abs, kArm64I32x4Abs)                             \
   V(I16x8SConvertI8x16Low, kArm64I16x8SConvertI8x16Low)   \
   V(I16x8SConvertI8x16High, kArm64I16x8SConvertI8x16High) \
   V(I16x8Neg, kArm64I16x8Neg)                             \
   V(I16x8UConvertI8x16Low, kArm64I16x8UConvertI8x16Low)   \
   V(I16x8UConvertI8x16High, kArm64I16x8UConvertI8x16High) \
+  V(I16x8Abs, kArm64I16x8Abs)                             \
   V(I8x16Neg, kArm64I8x16Neg)                             \
+  V(I8x16Abs, kArm64I8x16Abs)                             \
   V(S128Not, kArm64S128Not)                               \
   V(S1x2AnyTrue, kArm64S1x2AnyTrue)                       \
   V(S1x2AllTrue, kArm64S1x2AllTrue)                       \

src/compiler/backend/instruction-selector.cc

@@ -2627,9 +2627,6 @@ void InstructionSelector::VisitI64x2ReplaceLaneI32Pair(Node* node) {
 #endif  // !V8_TARGET_ARCH_IA32
 
 #if !V8_TARGET_ARCH_X64
-void InstructionSelector::VisitI8x16Abs(Node* node) { UNIMPLEMENTED(); }
-void InstructionSelector::VisitI16x8Abs(Node* node) { UNIMPLEMENTED(); }
-void InstructionSelector::VisitI32x4Abs(Node* node) { UNIMPLEMENTED(); }
 #if !V8_TARGET_ARCH_ARM64
 void InstructionSelector::VisitI64x2Splat(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitI64x2ExtractLane(Node* node) { UNIMPLEMENTED(); }
@@ -2646,6 +2643,9 @@ void InstructionSelector::VisitF64x2Qfma(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF64x2Qfms(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF32x4Qfma(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitF32x4Qfms(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitI8x16Abs(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitI16x8Abs(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitI32x4Abs(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_ARM64
 void InstructionSelector::VisitI64x2MinS(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitI64x2MaxS(Node* node) { UNIMPLEMENTED(); }

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1824,11 +1824,11 @@ WASM_SIMD_TEST(I32x4Neg) {
                    base::NegateWithWraparound);
 }
 
-#if V8_TARGET_ARCH_X64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 WASM_SIMD_TEST_NO_LOWERING(I32x4Abs) {
   RunI32x4UnOpTest(execution_tier, lower_simd, kExprI32x4Abs, Abs);
 }
-#endif
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 
 WASM_SIMD_TEST(S128Not) {
   RunI32x4UnOpTest(execution_tier, lower_simd, kExprS128Not, Not);
@@ -2089,11 +2089,11 @@ WASM_SIMD_TEST(I16x8Neg) {
                    base::NegateWithWraparound);
 }
 
-#if V8_TARGET_ARCH_X64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 WASM_SIMD_TEST_NO_LOWERING(I16x8Abs) {
   RunI16x8UnOpTest(execution_tier, lower_simd, kExprI16x8Abs, Abs);
 }
-#endif
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 
 template <typename T = int16_t, typename OpType = T (*)(T, T)>
 void RunI16x8BinOpTest(ExecutionTier execution_tier, LowerSimd lower_simd,
@@ -2296,11 +2296,11 @@ WASM_SIMD_TEST(I8x16Neg) {
                    base::NegateWithWraparound);
 }
 
-#if V8_TARGET_ARCH_X64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 WASM_SIMD_TEST_NO_LOWERING(I8x16Abs) {
   RunI8x16UnOpTest(execution_tier, lower_simd, kExprI8x16Abs, Abs);
 }
-#endif
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 
 // Tests both signed and unsigned conversion from I16x8 (packing).
 WASM_SIMD_TEST(I8x16ConvertI16x8) {