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Commit 83e66947 authored by bjaideep's avatar bjaideep Committed by Commit bot
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PPC/s390: [wasm] Trim graph before scheduling. 

Port 99023682

Original commit message:

    The scheduler expects a trimmed graph, so we have to trim the graph
    before scheduling.

R=ahaas@chromium.org, joransiu@ca.ibm.com, jyan@ca.ibm.com, michael_dawson@ca.ibm.com, mbrandy@us.ibm.com

BUG=
LOG=N

Review-Url: https://chromiumcodereview.appspot.com/2431093004
Cr-Commit-Position: refs/heads/master@{#40475}
parent 57b14b06
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Showing with 161 additions and 83 deletions
src/compiler/ppc/code-generator-ppc.cc
View file @ 83e66947
......@@ -1241,39 +1241,46 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ mulhwu(i.OutputRegister(1), i.InputRegister(0), i.InputRegister(2));
__ add(i.OutputRegister(1), i.OutputRegister(1), i.TempRegister(0));
break;
case kPPC_ShiftLeftPair:
case kPPC_ShiftLeftPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftLeftPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
__ ShiftLeftPair(i.OutputRegister(0), second_output, i.InputRegister(0),
i.InputRegister(1), i.InputInt32(2));
} else {
__ ShiftLeftPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1), kScratchReg,
i.InputRegister(2));
__ ShiftLeftPair(i.OutputRegister(0), second_output, i.InputRegister(0),
i.InputRegister(1), kScratchReg, i.InputRegister(2));
}
break;
case kPPC_ShiftRightPair:
}
case kPPC_ShiftRightPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1), kScratchReg,
i.InputRegister(2));
}
break;
case kPPC_ShiftRightAlgPair:
}
case kPPC_ShiftRightAlgPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightAlgPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightAlgPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightAlgPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightAlgPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
kScratchReg, i.InputRegister(2));
}
break;
}
#endif
case kPPC_RotRight32:
if (HasRegisterInput(instr, 1)) {
......
src/compiler/ppc/instruction-selector-ppc.cc
View file @ 83e66947
......@@ -810,9 +810,11 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
#if !V8_TARGET_ARCH_PPC64
void VisitPairBinop(InstructionSelector* selector, InstructionCode opcode,
Node* node) {
InstructionCode opcode2, Node* node) {
PPCOperandGenerator g(selector);
Node* projection1 = NodeProperties::FindProjection(node, 1);
if (projection1) {
// We use UseUniqueRegister here to avoid register sharing with the output
// registers.
InstructionOperand inputs[] = {
......@@ -824,22 +826,31 @@ void VisitPairBinop(InstructionSelector* selector, InstructionCode opcode,
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
selector->Emit(opcode, 2, outputs, 4, inputs);
} else {
// The high word of the result is not used, so we emit the standard 32 bit
// instruction.
selector->Emit(opcode2, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(2)));
}
}
void InstructionSelector::VisitInt32PairAdd(Node* node) {
VisitPairBinop(this, kPPC_AddPair, node);
VisitPairBinop(this, kPPC_AddPair, kPPC_Add, node);
}
void InstructionSelector::VisitInt32PairSub(Node* node) {
VisitPairBinop(this, kPPC_SubPair, node);
VisitPairBinop(this, kPPC_SubPair, kPPC_Sub, node);
}
void InstructionSelector::VisitInt32PairMul(Node* node) {
PPCOperandGenerator g(this);
Node* projection1 = NodeProperties::FindProjection(node, 1);
if (projection1) {
InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)),
g.UseUniqueRegister(node->InputAt(2)),
g.UseRegister(node->InputAt(3))};
g.UseUniqueRegister(node->InputAt(3))};
InstructionOperand outputs[] = {
g.DefineAsRegister(node),
......@@ -848,11 +859,21 @@ void InstructionSelector::VisitInt32PairMul(Node* node) {
InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()};
Emit(kPPC_MulPair, 2, outputs, 4, inputs, 2, temps);
} else {
// The high word of the result is not used, so we emit the standard 32 bit
// instruction.
Emit(kPPC_Mul32, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(2)));
}
}
namespace {
// Shared routine for multiple shift operations.
void VisitPairShift(InstructionSelector* selector, InstructionCode opcode,
Node* node) {
PPCOperandGenerator g(selector);
// We use g.UseUniqueRegister here to guarantee that there is
// no register aliasing of input registers with output registers.
Int32Matcher m(node->InputAt(2));
InstructionOperand shift_operand;
if (m.HasValue()) {
......@@ -861,16 +882,27 @@ void VisitPairShift(InstructionSelector* selector, InstructionCode opcode,
shift_operand = g.UseUniqueRegister(m.node());
}
InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)),
InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)),
shift_operand};
InstructionOperand outputs[] = {
g.DefineSameAsFirst(node),
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
Node* projection1 = NodeProperties::FindProjection(node, 1);
selector->Emit(opcode, 2, outputs, 3, inputs);
InstructionOperand outputs[2];
InstructionOperand temps[1];
int32_t output_count = 0;
int32_t temp_count = 0;
outputs[output_count++] = g.DefineAsRegister(node);
if (projection1) {
outputs[output_count++] = g.DefineAsRegister(projection1);
} else {
temps[temp_count++] = g.TempRegister();
}
selector->Emit(opcode, output_count, outputs, 3, inputs, temp_count, temps);
}
} // namespace
void InstructionSelector::VisitWord32PairShl(Node* node) {
VisitPairShift(this, kPPC_ShiftLeftPair, node);
......
src/compiler/s390/code-generator-s390.cc
View file @ 83e66947
......@@ -1159,39 +1159,46 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ lr(i.OutputRegister(0), r1);
__ srag(i.OutputRegister(1), r1, Operand(32));
break;
case kS390_ShiftLeftPair:
case kS390_ShiftLeftPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftLeftPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
__ ShiftLeftPair(i.OutputRegister(0), second_output, i.InputRegister(0),
i.InputRegister(1), i.InputInt32(2));
} else {
__ ShiftLeftPair(i.OutputRegister(0), i.OutputRegister(1),
i.InputRegister(0), i.InputRegister(1), kScratchReg,
i.InputRegister(2));
__ ShiftLeftPair(i.OutputRegister(0), second_output, i.InputRegister(0),
i.InputRegister(1), kScratchReg, i.InputRegister(2));
}
break;
case kS390_ShiftRightPair:
}
case kS390_ShiftRightPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1), kScratchReg,
i.InputRegister(2));
}
break;
case kS390_ShiftRightArithPair:
}
case kS390_ShiftRightArithPair: {
Register second_output =
instr->OutputCount() >= 2 ? i.OutputRegister(1) : i.TempRegister(0);
if (instr->InputAt(2)->IsImmediate()) {
__ ShiftRightArithPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightArithPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
i.InputInt32(2));
} else {
__ ShiftRightArithPair(i.OutputRegister(0), i.OutputRegister(1),
__ ShiftRightArithPair(i.OutputRegister(0), second_output,
i.InputRegister(0), i.InputRegister(1),
kScratchReg, i.InputRegister(2));
}
break;
}
#endif
case kS390_RotRight32:
if (HasRegisterInput(instr, 1)) {
......
src/compiler/s390/instruction-selector-s390.cc
View file @ 83e66947
......@@ -835,10 +835,12 @@ void InstructionSelector::VisitWord32Sar(Node* node) {
}
#if !V8_TARGET_ARCH_S390X
void VisitPairBinop(InstructionSelector* selector, ArchOpcode opcode,
Node* node) {
void VisitPairBinop(InstructionSelector* selector, InstructionCode opcode,
InstructionCode opcode2, Node* node) {
S390OperandGenerator g(selector);
Node* projection1 = NodeProperties::FindProjection(node, 1);
if (projection1) {
// We use UseUniqueRegister here to avoid register sharing with the output
// registers.
InstructionOperand inputs[] = {
......@@ -850,18 +852,27 @@ void VisitPairBinop(InstructionSelector* selector, ArchOpcode opcode,
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
selector->Emit(opcode, 2, outputs, 4, inputs);
} else {
// The high word of the result is not used, so we emit the standard 32 bit
// instruction.
selector->Emit(opcode2, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(2)));
}
}
void InstructionSelector::VisitInt32PairAdd(Node* node) {
VisitPairBinop(this, kS390_AddPair, node);
VisitPairBinop(this, kS390_AddPair, kS390_Add32, node);
}
void InstructionSelector::VisitInt32PairSub(Node* node) {
VisitPairBinop(this, kS390_SubPair, node);
VisitPairBinop(this, kS390_SubPair, kS390_Sub32, node);
}
void InstructionSelector::VisitInt32PairMul(Node* node) {
S390OperandGenerator g(this);
Node* projection1 = NodeProperties::FindProjection(node, 1);
if (projection1) {
InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)),
g.UseUniqueRegister(node->InputAt(2)),
......@@ -872,11 +883,21 @@ void InstructionSelector::VisitInt32PairMul(Node* node) {
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
Emit(kS390_MulPair, 2, outputs, 4, inputs);
} else {
// The high word of the result is not used, so we emit the standard 32 bit
// instruction.
Emit(kS390_Mul32, g.DefineSameAsFirst(node),
g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(2)));
}
}
void VisitPairShift(InstructionSelector* selector, ArchOpcode opcode,
namespace {
// Shared routine for multiple shift operations.
void VisitPairShift(InstructionSelector* selector, InstructionCode opcode,
Node* node) {
S390OperandGenerator g(selector);
// We use g.UseUniqueRegister here to guarantee that there is
// no register aliasing of input registers with output registers.
Int32Matcher m(node->InputAt(2));
InstructionOperand shift_operand;
if (m.HasValue()) {
......@@ -885,16 +906,27 @@ void VisitPairShift(InstructionSelector* selector, ArchOpcode opcode,
shift_operand = g.UseUniqueRegister(m.node());
}
InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)),
InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
g.UseUniqueRegister(node->InputAt(1)),
shift_operand};
InstructionOperand outputs[] = {
g.DefineSameAsFirst(node),
g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
Node* projection1 = NodeProperties::FindProjection(node, 1);
selector->Emit(opcode, 2, outputs, 3, inputs);
InstructionOperand outputs[2];
InstructionOperand temps[1];
int32_t output_count = 0;
int32_t temp_count = 0;
outputs[output_count++] = g.DefineAsRegister(node);
if (projection1) {
outputs[output_count++] = g.DefineAsRegister(projection1);
} else {
temps[temp_count++] = g.TempRegister();
}
selector->Emit(opcode, output_count, outputs, 3, inputs, temp_count, temps);
}
} // namespace
void InstructionSelector::VisitWord32PairShl(Node* node) {
VisitPairShift(this, kS390_ShiftLeftPair, node);
......
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