Commit 83729f18 authored by Michael Starzinger's avatar Michael Starzinger Committed by Commit Bot

[turbofan][cleanup] Remove dead ExplicitOperand class.

R=mvstanton@chromium.org
BUG=v8:9396

Change-Id: Iaf1f6af19d3c4236c6f1c4b215b90b2e390e81d3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1789297
Commit-Queue: Michael Starzinger <mstarzinger@chromium.org>
Reviewed-by: 's avatarZhi An Ng <zhin@chromium.org>
Reviewed-by: 's avatarMichael Stanton <mvstanton@chromium.org>
Cr-Commit-Position: refs/heads/master@{#63631}
parent 3951a351
......@@ -193,17 +193,6 @@ class OperandGenerator {
reg.code(), GetVReg(node)));
}
InstructionOperand UseExplicit(LinkageLocation location) {
MachineRepresentation rep = InstructionSequence::DefaultRepresentation();
if (location.IsRegister()) {
return ExplicitOperand(LocationOperand::REGISTER, rep,
location.AsRegister());
} else {
return ExplicitOperand(LocationOperand::STACK_SLOT, rep,
location.GetLocation());
}
}
InstructionOperand UseImmediate(int immediate) {
return sequence()->AddImmediate(Constant(immediate));
}
......
......@@ -168,7 +168,6 @@ std::ostream& operator<<(std::ostream& os, const InstructionOperand& op) {
return os << "[immediate:" << imm.indexed_value() << "]";
}
}
case InstructionOperand::EXPLICIT:
case InstructionOperand::ALLOCATED: {
LocationOperand allocated = LocationOperand::cast(op);
if (op.IsStackSlot()) {
......@@ -192,9 +191,6 @@ std::ostream& operator<<(std::ostream& os, const InstructionOperand& op) {
os << "[" << Simd128Register::from_code(allocated.register_code())
<< "|R";
}
if (allocated.IsExplicit()) {
os << "|E";
}
switch (allocated.representation()) {
case MachineRepresentation::kNone:
os << "|-";
......@@ -294,17 +290,6 @@ void ParallelMove::PrepareInsertAfter(
if (replacement != nullptr) move->set_source(replacement->source());
}
ExplicitOperand::ExplicitOperand(LocationKind kind, MachineRepresentation rep,
int index)
: LocationOperand(EXPLICIT, kind, rep, index) {
DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(rep),
GetRegConfig()->IsAllocatableGeneralCode(index));
DCHECK_IMPLIES(kind == REGISTER && rep == MachineRepresentation::kFloat32,
GetRegConfig()->IsAllocatableFloatCode(index));
DCHECK_IMPLIES(kind == REGISTER && (rep == MachineRepresentation::kFloat64),
GetRegConfig()->IsAllocatableDoubleCode(index));
}
Instruction::Instruction(InstructionCode opcode)
: opcode_(opcode),
bit_field_(OutputCountField::encode(0) | InputCountField::encode(0) |
......
......@@ -43,9 +43,8 @@ class V8_EXPORT_PRIVATE InstructionOperand {
CONSTANT,
IMMEDIATE,
// Location operand kinds.
EXPLICIT,
ALLOCATED,
FIRST_LOCATION_OPERAND_KIND = EXPLICIT
FIRST_LOCATION_OPERAND_KIND = ALLOCATED
// Location operand kinds must be last.
};
......@@ -68,11 +67,6 @@ class V8_EXPORT_PRIVATE InstructionOperand {
// embedded directly in instructions, e.g. small integers and on some
// platforms Objects.
INSTRUCTION_OPERAND_PREDICATE(Immediate, IMMEDIATE)
// ExplicitOperands do not participate in register allocation. They are
// created by the instruction selector for direct access to registers and
// stack slots, completely bypassing the register allocator. They are never
// associated with a virtual register
INSTRUCTION_OPERAND_PREDICATE(Explicit, EXPLICIT)
// AllocatedOperands are registers or stack slots that are assigned by the
// register allocator and are always associated with a virtual register.
INSTRUCTION_OPERAND_PREDICATE(Allocated, ALLOCATED)
......@@ -515,19 +509,6 @@ class LocationOperand : public InstructionOperand {
using IndexField = BitField64<int32_t, 35, 29>;
};
class V8_EXPORT_PRIVATE ExplicitOperand
: public NON_EXPORTED_BASE(LocationOperand) {
public:
ExplicitOperand(LocationKind kind, MachineRepresentation rep, int index);
static ExplicitOperand* New(Zone* zone, LocationKind kind,
MachineRepresentation rep, int index) {
return InstructionOperand::New(zone, ExplicitOperand(kind, rep, index));
}
INSTRUCTION_OPERAND_CASTS(ExplicitOperand, EXPLICIT)
};
class AllocatedOperand : public LocationOperand {
public:
AllocatedOperand(LocationKind kind, MachineRepresentation rep, int index)
......@@ -643,7 +624,7 @@ uint64_t InstructionOperand::GetCanonicalizedValue() const {
}
return InstructionOperand::KindField::update(
LocationOperand::RepresentationField::update(this->value_, canonical),
LocationOperand::EXPLICIT);
LocationOperand::ALLOCATED);
}
return this->value_;
}
......
......@@ -92,7 +92,7 @@ RegisterAllocatorVerifier::RegisterAllocatorVerifier(
void RegisterAllocatorVerifier::VerifyInput(
const OperandConstraint& constraint) {
CHECK_NE(kSameAsFirst, constraint.type_);
if (constraint.type_ != kImmediate && constraint.type_ != kExplicit) {
if (constraint.type_ != kImmediate) {
CHECK_NE(InstructionOperand::kInvalidVirtualRegister,
constraint.virtual_register_);
}
......@@ -102,14 +102,12 @@ void RegisterAllocatorVerifier::VerifyTemp(
const OperandConstraint& constraint) {
CHECK_NE(kSameAsFirst, constraint.type_);
CHECK_NE(kImmediate, constraint.type_);
CHECK_NE(kExplicit, constraint.type_);
CHECK_NE(kConstant, constraint.type_);
}
void RegisterAllocatorVerifier::VerifyOutput(
const OperandConstraint& constraint) {
CHECK_NE(kImmediate, constraint.type_);
CHECK_NE(kExplicit, constraint.type_);
CHECK_NE(InstructionOperand::kInvalidVirtualRegister,
constraint.virtual_register_);
}
......@@ -149,8 +147,6 @@ void RegisterAllocatorVerifier::BuildConstraint(const InstructionOperand* op,
constraint->type_ = kConstant;
constraint->value_ = ConstantOperand::cast(op)->virtual_register();
constraint->virtual_register_ = constraint->value_;
} else if (op->IsExplicit()) {
constraint->type_ = kExplicit;
} else if (op->IsImmediate()) {
const ImmediateOperand* imm = ImmediateOperand::cast(op);
int value = imm->type() == ImmediateOperand::INLINE ? imm->inline_value()
......@@ -235,9 +231,6 @@ void RegisterAllocatorVerifier::CheckConstraint(
case kFPRegister:
CHECK_WITH_MSG(op->IsFPRegister(), caller_info_);
return;
case kExplicit:
CHECK_WITH_MSG(op->IsExplicit(), caller_info_);
return;
case kFixedRegister:
case kRegisterAndSlot:
CHECK_WITH_MSG(op->IsRegister(), caller_info_);
......@@ -503,8 +496,7 @@ void RegisterAllocatorVerifier::VerifyGapMoves() {
instr_constraint.operand_constraints_;
size_t count = 0;
for (size_t i = 0; i < instr->InputCount(); ++i, ++count) {
if (op_constraints[count].type_ == kImmediate ||
op_constraints[count].type_ == kExplicit) {
if (op_constraints[count].type_ == kImmediate) {
continue;
}
int virtual_register = op_constraints[count].virtual_register_;
......
......@@ -188,7 +188,6 @@ class RegisterAllocatorVerifier final : public ZoneObject {
kRegisterOrSlot,
kRegisterOrSlotFP,
kRegisterOrSlotOrConstant,
kExplicit,
kSameAsFirst,
kRegisterAndSlot
};
......
......@@ -317,7 +317,6 @@ UsePositionHintType UsePosition::HintTypeForOperand(
switch (op.kind()) {
case InstructionOperand::CONSTANT:
case InstructionOperand::IMMEDIATE:
case InstructionOperand::EXPLICIT:
return UsePositionHintType::kNone;
case InstructionOperand::UNALLOCATED:
return UsePositionHintType::kUnresolved;
......@@ -1940,8 +1939,8 @@ void ConstraintBuilder::MeetConstraintsBefore(int instr_index) {
// Handle fixed input operands of second instruction.
for (size_t i = 0; i < second->InputCount(); i++) {
InstructionOperand* input = second->InputAt(i);
if (input->IsImmediate() || input->IsExplicit()) {
continue; // Ignore immediates and explicitly reserved registers.
if (input->IsImmediate()) {
continue; // Ignore immediates.
}
UnallocatedOperand* cur_input = UnallocatedOperand::cast(input);
if (cur_input->HasFixedPolicy()) {
......@@ -2323,8 +2322,8 @@ void LiveRangeBuilder::ProcessInstructions(const InstructionBlock* block,
for (size_t i = 0; i < instr->InputCount(); i++) {
InstructionOperand* input = instr->InputAt(i);
if (input->IsImmediate() || input->IsExplicit()) {
continue; // Ignore immediates and explicitly reserved registers.
if (input->IsImmediate()) {
continue; // Ignore immediates.
}
LifetimePosition use_pos;
if (input->IsUnallocated() &&
......@@ -2504,10 +2503,10 @@ void LiveRangeBuilder::ProcessPhis(const InstructionBlock* block,
predecessor_hint_preference |= kNotDeferredBlockPreference;
}
// - Prefer hints from allocated (or explicit) operands.
// - Prefer hints from allocated operands.
//
// Already-allocated or explicit operands are typically assigned using
// the parallel moves on the last instruction. For example:
// Already-allocated operands are typically assigned using the parallel
// moves on the last instruction. For example:
//
// gap (v101 = [x0|R|w32]) (v100 = v101)
// ArchJmp
......@@ -2515,7 +2514,7 @@ void LiveRangeBuilder::ProcessPhis(const InstructionBlock* block,
// phi: v100 = v101 v102
//
// We have already found the END move, so look for a matching START move
// from an allocated (or explicit) operand.
// from an allocated operand.
//
// Note that we cannot simply look up data()->live_ranges()[vreg] here
// because the live ranges are still being built when this function is
......@@ -2527,7 +2526,7 @@ void LiveRangeBuilder::ProcessPhis(const InstructionBlock* block,
for (MoveOperands* move : *moves) {
InstructionOperand& to = move->destination();
if (predecessor_hint->Equals(to)) {
if (move->source().IsAllocated() || move->source().IsExplicit()) {
if (move->source().IsAllocated()) {
predecessor_hint_preference |= kMoveIsAllocatedPreference;
}
break;
......
......@@ -1055,15 +1055,9 @@ std::ostream& operator<<(std::ostream& os, const InstructionOperandAsJSON& o) {
}
break;
}
case InstructionOperand::EXPLICIT:
case InstructionOperand::ALLOCATED: {
const LocationOperand* allocated = LocationOperand::cast(op);
os << "\"type\": ";
if (allocated->IsExplicit()) {
os << "\"explicit\", ";
} else {
os << "\"allocated\", ";
}
os << "\"type\": \"allocated\", ";
os << "\"text\": \"";
if (op->IsStackSlot()) {
os << "stack:" << allocated->index();
......
......@@ -353,7 +353,7 @@ class ParallelMoveCreator : public HandleAndZoneScope {
};
int index = rng_->NextInt(kMaxIndex);
// destination can't be Constant.
switch (rng_->NextInt(is_source ? 5 : 4)) {
switch (rng_->NextInt(is_source ? 3 : 2)) {
case 0:
return AllocatedOperand(LocationOperand::STACK_SLOT, rep,
GetValidSlotIndex(rep, index));
......@@ -361,12 +361,6 @@ class ParallelMoveCreator : public HandleAndZoneScope {
return AllocatedOperand(LocationOperand::REGISTER, rep,
GetValidRegisterCode(rep, index));
case 2:
return ExplicitOperand(LocationOperand::REGISTER, rep,
GetValidRegisterCode(rep, 1));
case 3:
return ExplicitOperand(LocationOperand::STACK_SLOT, rep,
GetValidSlotIndex(rep, index));
case 4:
return ConstantOperand(index);
}
UNREACHABLE();
......
......@@ -47,7 +47,6 @@ class InstructionSequenceTest : public TestWithIsolateAndZone {
kFixedRegister,
kSlot,
kFixedSlot,
kExplicit,
kImmediate,
kNone,
kConstant,
......@@ -75,17 +74,6 @@ class InstructionSequenceTest : public TestWithIsolateAndZone {
static TestOperand Same() { return TestOperand(kSameAsFirst); }
static TestOperand ExplicitReg(int index) {
TestOperandType type = kExplicit;
return TestOperand(type, index);
}
static TestOperand ExplicitFPReg(int index,
MachineRepresentation rep = kFloat64) {
TestOperandType type = kExplicit;
return TestOperand(type, index, rep);
}
static TestOperand Reg(VReg vreg, int index = kNoValue) {
TestOperandType type = (index == kNoValue) ? kRegister : kFixedRegister;
return TestOperand(type, vreg, index);
......
......@@ -83,11 +83,6 @@ class MoveOptimizerTest : public InstructionSequenceTest {
CHECK(0 <= op.value_ && op.value_ < GetNumRegs(rep));
return AllocatedOperand(LocationOperand::REGISTER, rep, op.value_);
}
case kExplicit: {
MachineRepresentation rep = GetCanonicalRep(op);
CHECK(0 <= op.value_ && op.value_ < GetNumRegs(rep));
return ExplicitOperand(LocationOperand::REGISTER, rep, op.value_);
}
default:
break;
}
......@@ -123,45 +118,6 @@ TEST_F(MoveOptimizerTest, RemovesRedundant) {
CHECK(Contains(move, FPReg(kF32_1, kFloat32), FPReg(kF32_2, kFloat32)));
}
TEST_F(MoveOptimizerTest, RemovesRedundantExplicit) {
int index1 = GetAllocatableCode(0);
int index2 = GetAllocatableCode(1);
int s128_1 = GetAllocatableCode(kS128_1, kSimd128);
int s128_2 = GetAllocatableCode(kS128_2, kSimd128);
int f64_1 = GetAllocatableCode(kF64_1, kFloat64);
int f64_2 = GetAllocatableCode(kF64_2, kFloat64);
int f32_1 = GetAllocatableCode(kF32_1, kFloat32);
int f32_2 = GetAllocatableCode(kF32_2, kFloat32);
StartBlock();
auto first_instr = EmitNop();
auto last_instr = EmitNop();
AddMove(first_instr, Reg(index1), ExplicitReg(index2));
AddMove(last_instr, Reg(index2), Reg(index1));
AddMove(first_instr, FPReg(s128_1, kSimd128),
ExplicitFPReg(s128_2, kSimd128));
AddMove(last_instr, FPReg(s128_2, kSimd128), FPReg(s128_1, kSimd128));
AddMove(first_instr, FPReg(f64_1, kFloat64), ExplicitFPReg(f64_2, kFloat64));
AddMove(last_instr, FPReg(f64_2, kFloat64), FPReg(f64_1, kFloat64));
AddMove(first_instr, FPReg(f32_1, kFloat32), ExplicitFPReg(f32_2, kFloat32));
AddMove(last_instr, FPReg(f32_2, kFloat32), FPReg(f32_1, kFloat32));
EndBlock(Last());
Optimize();
CHECK_EQ(0, NonRedundantSize(first_instr->parallel_moves()[0]));
auto move = last_instr->parallel_moves()[0];
CHECK_EQ(4, NonRedundantSize(move));
CHECK(Contains(move, Reg(index1), ExplicitReg(index2)));
CHECK(
Contains(move, FPReg(s128_1, kSimd128), ExplicitFPReg(s128_2, kSimd128)));
CHECK(Contains(move, FPReg(f64_1, kFloat64), ExplicitFPReg(f64_2, kFloat64)));
CHECK(Contains(move, FPReg(f32_1, kFloat32), ExplicitFPReg(f32_2, kFloat32)));
}
TEST_F(MoveOptimizerTest, SplitsConstants) {
StartBlock();
EndBlock(Last());
......
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