X87: [wasm] Int64Lowering of Int64Sub on ia32 and arm.

  port 33c08596 (r34808)

  original commit message:
  Int64Sub is lowered to a new turbofan operator, Int32SubPair. The new
  operator takes 4 inputs an generates 2 outputs. The inputs are the low
  word of the left input, high word of the left input, the low word of the
  right input, and high word of the right input. The ouputs are the low
  and high word of the result of the subtraction.

  The implementation is very similar to the implementation of Int64Add.

  @v8-arm-ports: please take a careful look at the implementation of sbc
  in the simulator

BUG=

Review URL: https://codereview.chromium.org/1812753003

Cr-Commit-Position: refs/heads/master@{#34844}

src/compiler/x87/code-generator-x87.cc

@@ -787,6 +787,31 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       }
       break;
     }
+    case kX87SubPair: {
+      // i.OutputRegister(0) == i.InputRegister(0) ... left low word.
+      // i.InputRegister(1) ... left high word.
+      // i.InputRegister(2) ... right low word.
+      // i.InputRegister(3) ... right high word.
+      bool use_temp = false;
+      if (i.OutputRegister(0).code() == i.InputRegister(1).code() ||
+          i.OutputRegister(0).code() == i.InputRegister(3).code()) {
+        // We cannot write to the output register directly, because it would
+        // overwrite an input for adc. We have to use the temp register.
+        use_temp = true;
+        __ Move(i.TempRegister(0), i.InputRegister(0));
+        __ sub(i.TempRegister(0), i.InputRegister(2));
+      } else {
+        __ sub(i.OutputRegister(0), i.InputRegister(2));
+      }
+      __ sbb(i.InputRegister(1), Operand(i.InputRegister(3)));
+      if (i.OutputRegister(1).code() != i.InputRegister(1).code()) {
+        __ Move(i.OutputRegister(1), i.InputRegister(1));
+      }
+      if (use_temp) {
+        __ Move(i.OutputRegister(0), i.TempRegister(0));
+      }
+      break;
+    }
     case kX87ShlPair:
       if (HasImmediateInput(instr, 2)) {
         __ ShlPair(i.InputRegister(1), i.InputRegister(0), i.InputInt6(2));

src/compiler/x87/instruction-codes-x87.h

@@ -32,6 +32,7 @@ namespace compiler {
   V(X87Shr)                        \
   V(X87Sar)                        \
   V(X87AddPair)                    \
+  V(X87SubPair)                    \
   V(X87ShlPair)                    \
   V(X87ShrPair)                    \
   V(X87SarPair)                    \

src/compiler/x87/instruction-selector-x87.cc

@@ -562,7 +562,23 @@ void InstructionSelector::VisitInt32PairAdd(Node* node) {
   Emit(kX87AddPair, 2, outputs, 4, inputs, 1, temps);
 }
 
-void InstructionSelector::VisitInt32PairSub(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitInt32PairSub(Node* node) {
+  X87OperandGenerator g(this);
+
+  // We use UseUniqueRegister here to avoid register sharing with the temp
+  // register.
+  InstructionOperand inputs[] = {
+      g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)),
+      g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))};
+
+  InstructionOperand outputs[] = {
+      g.DefineSameAsFirst(node),
+      g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
+
+  InstructionOperand temps[] = {g.TempRegister()};
+
+  Emit(kX87SubPair, 2, outputs, 4, inputs, 1, temps);
+}
 
 void InstructionSelector::VisitWord32PairShl(Node* node) {
   X87OperandGenerator g(this);