PPC: [wasm-simd] Implement simd shuffle

Also changing the wording of comment under s390
instruction-selector to match PPC.

Change-Id: I8fa77cbf51872792acd0e89915cb11d4759d51f5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2305850Reviewed-by: Joran Siu <joransiu@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68948}

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -3155,6 +3155,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                  i.InputSimd128Register(1));
       break;
     }
+    case kPPC_S8x16Shuffle: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src0 = i.InputSimd128Register(0),
+                      src1 = i.InputSimd128Register(1);
+      __ mov(r0, Operand(make_uint64(i.InputUint32(3), i.InputUint32(2))));
+      __ mov(ip, Operand(make_uint64(i.InputUint32(5), i.InputUint32(4))));
+      // Need to maintain 16 byte alignment for lvx.
+      __ mr(kScratchReg, sp);
+      __ ClearRightImm(
+          sp, sp,
+          Operand(base::bits::WhichPowerOfTwo(16)));  // equivalent to &= -16
+      __ addi(sp, sp, Operand(-16));
+      __ StoreP(r0, MemOperand(sp, 0));
+      __ StoreP(ip, MemOperand(sp, 8));
+      __ li(r0, Operand(0));
+      __ lvx(kScratchDoubleReg, MemOperand(sp, r0));
+      __ mr(sp, kScratchReg);
+      __ vperm(dst, src0, src1, kScratchDoubleReg);
+      break;
+    }
     case kPPC_StoreCompressTagged: {
       ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
       break;

src/compiler/backend/ppc/instruction-codes-ppc.h

@@ -322,6 +322,7 @@ namespace compiler {
   V(PPC_I8x16Abs)                    \
   V(PPC_I8x16SConvertI16x8)          \
   V(PPC_I8x16UConvertI16x8)          \
+  V(PPC_S8x16Shuffle)                \
   V(PPC_V64x2AnyTrue)                \
   V(PPC_V32x4AnyTrue)                \
   V(PPC_V16x8AnyTrue)                \

src/compiler/backend/ppc/instruction-scheduler-ppc.cc

@@ -245,6 +245,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_I8x16Abs:
     case kPPC_I8x16SConvertI16x8:
     case kPPC_I8x16UConvertI16x8:
+    case kPPC_S8x16Shuffle:
     case kPPC_V64x2AnyTrue:
     case kPPC_V32x4AnyTrue:
     case kPPC_V16x8AnyTrue:

src/compiler/backend/ppc/instruction-selector-ppc.cc

@@ -2334,6 +2334,31 @@ SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
 #undef SIMD_BOOL_LIST
 #undef SIMD_TYPES
 
+void InstructionSelector::VisitS8x16Shuffle(Node* node) {
+  uint8_t shuffle[kSimd128Size];
+  bool is_swizzle;
+  CanonicalizeShuffle(node, shuffle, &is_swizzle);
+  PPCOperandGenerator g(this);
+  Node* input0 = node->InputAt(0);
+  Node* input1 = node->InputAt(1);
+  // Remap the shuffle indices to match IBM lane numbering.
+  int max_index = 15;
+  int total_lane_count = 2 * kSimd128Size;
+  uint8_t shuffle_remapped[kSimd128Size];
+  for (int i = 0; i < kSimd128Size; i++) {
+    uint8_t current_index = shuffle[i];
+    shuffle_remapped[i] = (current_index <= max_index
+                               ? max_index - current_index
+                               : total_lane_count - current_index + max_index);
+  }
+  Emit(kPPC_S8x16Shuffle, g.DefineAsRegister(node), g.UseUniqueRegister(input0),
+       g.UseUniqueRegister(input1),
+       g.UseImmediate(Pack4Lanes(shuffle_remapped)),
+       g.UseImmediate(Pack4Lanes(shuffle_remapped + 4)),
+       g.UseImmediate(Pack4Lanes(shuffle_remapped + 8)),
+       g.UseImmediate(Pack4Lanes(shuffle_remapped + 12)));
+}
+
 void InstructionSelector::VisitS128Zero(Node* node) {
   PPCOperandGenerator g(this);
   Emit(kPPC_S128Zero, g.DefineAsRegister(node));
@@ -2419,8 +2444,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
 
-void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
-
 void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitF64x2Div(Node* node) { UNIMPLEMENTED(); }

src/compiler/backend/s390/instruction-selector-s390.cc

@@ -2841,8 +2841,7 @@ void InstructionSelector::VisitS8x16Shuffle(Node* node) {
   Node* input0 = node->InputAt(0);
   Node* input1 = node->InputAt(1);
 #ifdef V8_TARGET_BIG_ENDIAN
-  // input registers are each in reverse order, we will have to remap the
-  // shuffle indices
+  // Remap the shuffle indices to match IBM lane numbering.
   int max_index = 15;
   int total_lane_count = 2 * kSimd128Size;
   uint8_t shuffle_remapped[kSimd128Size];