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Commit 7e5d34bf authored by Yang Guo's avatar Yang Guo Committed by Commit Bot
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Revert "[ia32][wasm] Add F32x4AddHoriz, I32x4AddHoriz and I16x8AddHoriz" 

This reverts commit 9a0ccf4f.

Reason for revert: https://build.chromium.org/p/client.v8/builders/V8%20Linux%20-%20debug/builds/19794

Original change's description:
> [ia32][wasm] Add F32x4AddHoriz, I32x4AddHoriz and I16x8AddHoriz
> 
> Change-Id: Icdecfadbb1acc77d21a65d997f83c5f4db7c0780
> Reviewed-on: https://chromium-review.googlesource.com/942049
> Commit-Queue: Jing Bao <jing.bao@intel.com>
> Reviewed-by: Bill Budge <bbudge@chromium.org>
> Cr-Commit-Position: refs/heads/master@{#52203}

TBR=bbudge@chromium.org,mtrofin@chromium.org,bmeurer@chromium.org,jing.bao@intel.com

Change-Id: Iad906959b9fb1ffba02ce4286f15d51fef49b12d
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Reviewed-on: https://chromium-review.googlesource.com/979533Reviewed-by: 's avatarYang Guo <yangguo@chromium.org>
Commit-Queue: Yang Guo <yangguo@chromium.org>
Cr-Commit-Position: refs/heads/master@{#52206}
parent bba9ace3
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Showing with 18 additions and 51 deletions
src/compiler/ia32/code-generator-ia32.cc
View file @ 7e5d34bf
......@@ -1819,18 +1819,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(1));
break;
}
case kSSEF32x4AddHoriz: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSE3);
__ haddps(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXF32x4AddHoriz: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vhaddps(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEF32x4Sub: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ subps(i.OutputSimd128Register(), i.InputOperand(1));
......@@ -1986,18 +1974,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(1));
break;
}
case kSSEI32x4AddHoriz: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSSE3);
__ phaddd(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI32x4AddHoriz: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vphaddd(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI32x4Sub: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psubd(i.OutputSimd128Register(), i.InputOperand(1));
......@@ -2254,18 +2230,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputOperand(1));
break;
}
case kSSEI16x8AddHoriz: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
CpuFeatureScope sse_scope(tasm(), SSSE3);
__ phaddw(i.OutputSimd128Register(), i.InputOperand(1));
break;
}
case kAVXI16x8AddHoriz: {
CpuFeatureScope avx_scope(tasm(), AVX);
__ vphaddw(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputOperand(1));
break;
}
case kSSEI16x8Sub: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ psubw(i.OutputSimd128Register(), i.InputOperand(1));
......
src/compiler/ia32/instruction-codes-ia32.h
View file @ 7e5d34bf
......@@ -127,8 +127,6 @@ namespace compiler {
V(AVXF32x4Neg) \
V(SSEF32x4Add) \
V(AVXF32x4Add) \
V(SSEF32x4AddHoriz) \
V(AVXF32x4AddHoriz) \
V(SSEF32x4Sub) \
V(AVXF32x4Sub) \
V(SSEF32x4Mul) \
......@@ -156,8 +154,6 @@ namespace compiler {
V(AVXI32x4ShrS) \
V(SSEI32x4Add) \
V(AVXI32x4Add) \
V(SSEI32x4AddHoriz) \
V(AVXI32x4AddHoriz) \
V(SSEI32x4Sub) \
V(AVXI32x4Sub) \
V(SSEI32x4Mul) \
......@@ -197,8 +193,6 @@ namespace compiler {
V(AVXI16x8Add) \
V(SSEI16x8AddSaturateS) \
V(AVXI16x8AddSaturateS) \
V(SSEI16x8AddHoriz) \
V(AVXI16x8AddHoriz) \
V(SSEI16x8Sub) \
V(AVXI16x8Sub) \
V(SSEI16x8SubSaturateS) \
......
src/compiler/ia32/instruction-scheduler-ia32.cc
View file @ 7e5d34bf
......@@ -109,8 +109,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXF32x4Neg:
case kSSEF32x4Add:
case kAVXF32x4Add:
case kSSEF32x4AddHoriz:
case kAVXF32x4AddHoriz:
case kSSEF32x4Sub:
case kAVXF32x4Sub:
case kSSEF32x4Mul:
......@@ -138,8 +136,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXI32x4ShrS:
case kSSEI32x4Add:
case kAVXI32x4Add:
case kSSEI32x4AddHoriz:
case kAVXI32x4AddHoriz:
case kSSEI32x4Sub:
case kAVXI32x4Sub:
case kSSEI32x4Mul:
......@@ -179,8 +175,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kAVXI16x8Add:
case kSSEI16x8AddSaturateS:
case kAVXI16x8AddSaturateS:
case kSSEI16x8AddHoriz:
case kAVXI16x8AddHoriz:
case kSSEI16x8Sub:
case kAVXI16x8Sub:
case kSSEI16x8SubSaturateS:
......
src/compiler/ia32/instruction-selector-ia32.cc
View file @ 7e5d34bf
......@@ -1734,7 +1734,6 @@ VISIT_ATOMIC_BINOP(Xor)
#define SIMD_BINOP_LIST(V) \
V(F32x4Add) \
V(F32x4AddHoriz) \
V(F32x4Sub) \
V(F32x4Mul) \
V(F32x4Min) \
......@@ -1744,7 +1743,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(F32x4Lt) \
V(F32x4Le) \
V(I32x4Add) \
V(I32x4AddHoriz) \
V(I32x4Sub) \
V(I32x4Mul) \
V(I32x4MinS) \
......@@ -1759,7 +1757,6 @@ VISIT_ATOMIC_BINOP(Xor)
V(I32x4GeU) \
V(I16x8Add) \
V(I16x8AddSaturateS) \
V(I16x8AddHoriz) \
V(I16x8Sub) \
V(I16x8SubSaturateS) \
V(I16x8Mul) \
......
src/compiler/instruction-selector.cc
View file @ 7e5d34bf
......@@ -2327,6 +2327,8 @@ void InstructionSelector::VisitF32x4RecipApprox(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4RecipSqrtApprox(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitF32x4AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
......@@ -2342,6 +2344,12 @@ void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS
// && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_X64
void InstructionSelector::VisitI32x4AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS
// && !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_X64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) {
......@@ -2374,6 +2382,12 @@ void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS
// && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
......
test/cctest/wasm/test-run-wasm-simd.cc
View file @ 7e5d34bf
......@@ -1607,6 +1607,8 @@ void RunBinaryLaneOpTest(
}
}
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST(I32x4AddHoriz) {
RunBinaryLaneOpTest<int32_t>(lower_simd, kExprI32x4AddHoriz, {{1, 5, 9, 13}});
}
......@@ -1620,6 +1622,8 @@ WASM_SIMD_TEST(F32x4AddHoriz) {
RunBinaryLaneOpTest<float>(lower_simd, kExprF32x4AddHoriz,
{{1.0f, 5.0f, 9.0f, 13.0f}});
}
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_IA32
......
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