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Commit 7d9fb83c authored by Milad Fa's avatar Milad Fa Committed by Commit Bot
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PPC [simd]: Implement vbperm and specific sized load/stores on Sim 

Change-Id: I5608c6123433b1378d92c534e8f38dba68ac3d15
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2760778Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#73408}
parent fa350f4c
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Inline Side-by-side
Showing with 85 additions and 8 deletions
src/execution/ppc/simulator-ppc.cc
View file @ 7d9fb83c
......@@ -1388,6 +1388,9 @@ void Simulator::ExecuteBranchConditional(Instruction* instr, BCType type) {
}
// Vector instruction helpers.
#define GET_ADDRESS(a, b, a_val, b_val) \
intptr_t a_val = a == 0 ? 0 : get_register(a); \
intptr_t b_val = get_register(b);
#define DECODE_VX_INSTRUCTION(d, a, b, source_or_target) \
int d = instr->R##source_or_target##Value(); \
int a = instr->RAValue(); \
......@@ -2464,6 +2467,16 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
}
break;
}
case MTVSRDD: {
int xt = instr->RTValue();
int ra = instr->RAValue();
int rb = instr->RBValue();
set_simd_register_by_lane<int64_t>(
xt, 0, static_cast<int64_t>(get_register(ra)));
set_simd_register_by_lane<int64_t>(
xt, 1, static_cast<int64_t>(get_register(rb)));
break;
}
case MTVSRWA: {
DCHECK(!instr->Bit(0));
int frt = instr->RTValue();
......@@ -3869,8 +3882,7 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
// Vector instructions.
case LVX: {
DECODE_VX_INSTRUCTION(vrt, ra, rb, T)
intptr_t ra_val = ra == 0 ? 0 : get_register(ra);
intptr_t rb_val = get_register(rb);
GET_ADDRESS(ra, rb, ra_val, rb_val)
intptr_t addr = (ra_val + rb_val) & 0xFFFFFFFFFFFFFFF0;
simdr_t* ptr = reinterpret_cast<simdr_t*>(addr);
set_simd_register(vrt, *ptr);
......@@ -3878,8 +3890,7 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
}
case STVX: {
DECODE_VX_INSTRUCTION(vrs, ra, rb, S)
intptr_t ra_val = ra == 0 ? 0 : get_register(ra);
intptr_t rb_val = get_register(rb);
GET_ADDRESS(ra, rb, ra_val, rb_val)
__int128 vrs_val =
*(reinterpret_cast<__int128*>(get_simd_register(vrs).int8));
WriteQW((ra_val + rb_val) & 0xFFFFFFFFFFFFFFF0, vrs_val);
......@@ -3887,8 +3898,7 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
}
case LXVD: {
DECODE_VX_INSTRUCTION(xt, ra, rb, T)
intptr_t ra_val = ra == 0 ? 0 : get_register(ra);
intptr_t rb_val = get_register(rb);
GET_ADDRESS(ra, rb, ra_val, rb_val)
set_simd_register_by_lane<int64_t>(xt, 0, ReadDW(ra_val + rb_val));
set_simd_register_by_lane<int64_t>(
xt, 1, ReadDW(ra_val + rb_val + kSystemPointerSize));
......@@ -3896,13 +3906,60 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
}
case STXVD: {
DECODE_VX_INSTRUCTION(xs, ra, rb, S)
intptr_t ra_val = ra == 0 ? 0 : get_register(ra);
intptr_t rb_val = get_register(rb);
GET_ADDRESS(ra, rb, ra_val, rb_val)
WriteDW(ra_val + rb_val, get_simd_register_by_lane<int64_t>(xs, 0));
WriteDW(ra_val + rb_val + kSystemPointerSize,
get_simd_register_by_lane<int64_t>(xs, 1));
break;
}
case LXSIBZX: {
DECODE_VX_INSTRUCTION(xt, ra, rb, T)
GET_ADDRESS(ra, rb, ra_val, rb_val)
set_simd_register_by_lane<uint64_t>(xt, 0, ReadBU(ra_val + rb_val));
break;
}
case LXSIHZX: {
DECODE_VX_INSTRUCTION(xt, ra, rb, T)
GET_ADDRESS(ra, rb, ra_val, rb_val)
set_simd_register_by_lane<uint64_t>(xt, 0, ReadHU(ra_val + rb_val));
break;
}
case LXSIWZX: {
DECODE_VX_INSTRUCTION(xt, ra, rb, T)
GET_ADDRESS(ra, rb, ra_val, rb_val)
set_simd_register_by_lane<uint64_t>(xt, 0, ReadWU(ra_val + rb_val));
break;
}
case LXSDX: {
DECODE_VX_INSTRUCTION(xt, ra, rb, T)
GET_ADDRESS(ra, rb, ra_val, rb_val)
set_simd_register_by_lane<int64_t>(xt, 0, ReadDW(ra_val + rb_val));
break;
}
case STXSIBX: {
DECODE_VX_INSTRUCTION(xs, ra, rb, S)
GET_ADDRESS(ra, rb, ra_val, rb_val)
WriteB(ra_val + rb_val, get_simd_register_by_lane<int8_t>(xs, 7));
break;
}
case STXSIHX: {
DECODE_VX_INSTRUCTION(xs, ra, rb, S)
GET_ADDRESS(ra, rb, ra_val, rb_val)
WriteH(ra_val + rb_val, get_simd_register_by_lane<int16_t>(xs, 3));
break;
}
case STXSIWX: {
DECODE_VX_INSTRUCTION(xs, ra, rb, S)
GET_ADDRESS(ra, rb, ra_val, rb_val)
WriteW(ra_val + rb_val, get_simd_register_by_lane<int32_t>(xs, 1));
break;
}
case STXSDX: {
DECODE_VX_INSTRUCTION(xs, ra, rb, S)
GET_ADDRESS(ra, rb, ra_val, rb_val)
WriteDW(ra_val + rb_val, get_simd_register_by_lane<int64_t>(xs, 0));
break;
}
#define VSPLT(type) \
uint32_t uim = instr->Bits(20, 16); \
int vrt = instr->RTValue(); \
......@@ -4515,6 +4572,25 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
}
break;
}
case VBPERMQ: {
DECODE_VX_INSTRUCTION(t, a, b, T)
uint16_t result_bits = 0;
unsigned __int128 src_bits =
*(reinterpret_cast<__int128*>(get_simd_register(a).int8));
for (int i = 0; i < kSimd128Size; i++) {
result_bits <<= 1;
uint8_t selected_bit_index = get_simd_register_by_lane<uint8_t>(b, i);
if (selected_bit_index < (kSimd128Size * kBitsPerByte)) {
unsigned __int128 bit_value = (src_bits << selected_bit_index) >>
(kSimd128Size * kBitsPerByte - 1);
result_bits |= bit_value;
}
}
set_simd_register_by_lane<uint64_t>(t, 0, 0);
set_simd_register_by_lane<uint64_t>(t, 1, 0);
set_simd_register_by_lane<uint16_t>(t, 3, result_bits);
break;
}
#define VECTOR_FP_QF(type, sign) \
DECODE_VX_INSTRUCTION(t, a, b, T) \
FOR_EACH_LANE(i, type) { \
......@@ -4546,6 +4622,7 @@ void Simulator::ExecuteGeneric(Instruction* instr) {
#undef VECTOR_FP_QF
#undef FOR_EACH_LANE
#undef DECODE_VX_INSTRUCTION
#undef GET_ADDRESS
default: {
UNIMPLEMENTED();
break;
......
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